External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines

This topic provides high-level guidance for parameterizing the tabs in the Agilex™ 5 EMIF IP parameter editor.
Table 1.  EMIF Parameter Editor Guidelines
Parameter Editor Tab Guidelines
High Level Parameters

Ensure that you correctly enter the following parameters:

  • Data DQ Width
  • ECC DQ Width
  • Die DQ Width
  • CS (chip select) Width
  • Memory speed bin
  • Memory operating frequency
PHY

Allows you to set the following parameters:

  • PLL reference clock frequency.
  • AC placement.
  • Pin swizzle mapping.
  • Debug Toolkit enabling.
In addition, you can select the desired mode from Mainband Access Mode, to connect the EMIF IP to user logic:
  • Sunchronous fabric.
  • Asynchronous fabric.
Controller Setting

Set the controller parameters according to the desired configuration and behavior for your memory controller:

  • ECC autocorrection.
  • Data masking.
  • WDBI.
  • RDBI.
Memory Timing Setting Allows you to modify timing parameter settings.
Analog Properties Allows you to modify the termination, drive strength, and VREF settings.
Example Design The Example Design tab lets you select which HDL to use for the top-level files, and which file sets you want the design example to generate:
  • Synthesis.
  • Simulation.
  • Core clock frequency.
  • Core reference frequency.
You should make these selections before clicking the Generate Example Design... button. The generated design example is a complete EMIF system consisting of the EMIF IP and a driver to validate the memory interface.
Performance Monitor Enable performance monitor on all channels for measuring read/write transaction metrics.
Traffic Generator Program Allows you to specify the traffic pattern that you want to run:
  • Short mode.
  • Medium mode.
  • Long mode.
  • Infinite mode.
Figure 6. External Memory Interfaces IP Parameter Editor

For detailed information on individual parameters, refer to the appropriate protocol-specific chapter in the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs .

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