External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface

Table 9.  Lane Placement for x32 + ECC DDR4 Interface
Lane Number BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
DDR4_AC_TOP DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC3 sDO[0]
DQS Group Number in Byte Swizzling Notation 3 2 1 0 AC1 AC2 AC0 ECC
BYTE SWIZZLE 3 2 0 1 X X X ECC

In this example, BL7 cannot be swapped with other used DQS group. It is used as follows:

  • RUSER/WUSER Lane in x40 configuration
  • ECC Lane in x32 + ECC configuration

This example illustrates swizzling DQS group 1 (BL3) with DQS group 0 (BL2).

To achieve this swizzling, enter the following specifications in the Pin Swizzle Map under the PHY section:

BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,ECC;

In a DDR4 x32 + ECC configuration, the highest index DQS group is used as the ECC lane. We use PIN_SWIZZLE_CH0_ECC for swizzling the DQ pins within the ECC lane in this case. Note that the valid value for pin swizzling specification in the ECC lane is always 0-7 only.

Table 10.  Example of DQ Pin Swizzling in ECC Lane
Lane Pin Index Default Effective Pinout
BL7 95 MEM_DQ[39] MEM_DQ[36]
94 MEM_DQ[38] MEM_DQ[37]
93 MEM_DQ[37] MEM_DQ[38]
92 MEM_DQ[36] MEM_DQ[39]
91    
90 MEM_DM_N[4] MEM_DM_N[4]
89 MEM_DQS_C[4] MEM_DQS_C[4]
88 MEM_DQS_T[4] MEM_DQS_T[4]
87 MEM_DQ[35] MEM_DQ[34]
86 MEM_DQ[34] MEM_DQ[35]
85 MEM_DQ[33] MEM_DQ[32]
84 MEM_DQ[32] MEM_DQ[33]

To achieve the pin swizzling shown in the above table, enter the BYTE_SWIZZLE_CH0 specification in the Pin Swizzle Map under the PHY section: 

PIN_SWIZZLE_CH0_ECC=1,0,3,2,7,6,5,4;
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