External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration DDR4 with sDQ
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.3.5. Example: Byte Swizzling for Lockstep Configuration

In lockstep configuration, a DQ lane with a letter s prefix is used as RUSER/WUSER or ECC lane. This lane corresponds to the ECC lane in byte-swizzling notation; it cannot be swapped with other DQS lanes.
Note: Lockstep configuration is supported only on Agilex™ 5 D-Series devices.

DDR4 with sDQ

sDQ[0] maps to the RUSER/WUSER group. It corresponds to the ECC lane in byte-swizzling notation. Because the BYTE_SWIZZLE_CH0 specification can only accept 0,1,2,3,ECC and x, the group number for other DQS groups must be reduced by 1.

This example illustrates the swizzling of DQS group 3 (BL0) with DQS group 2 (BL1), and DQS group 1 (BL2) with DQS group 0 (BL3), respectively.

Table 11.  Lane Placement for x32 + ECC DDR4 Interface
Scheme BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
DDR4/5_AC_TOP DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC3 sDO[0]
DQS group number in byte swizzling notation 3 2 1 0 X X X ECC
After Byte Swizzle 3 2 0 1 X X X ECC

To achieve this swizzling above, enter the following BYTE_SWIZZLE_CH0 specification in Pin Swizzle Map under the PHY section: 

BYTE_SWIZZLE_CH0=2,3,0,1,X,X,X,ECC;

The method to swizzle the DQ pin within a group is the same for lockstep and nonlockstep configuration. Refer to the DQ Pin Swizzling Within DQS group for x32 DDR4 interface example for more information on how to configure DQ Pin Swizzling.

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