GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 8/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate

Each CPRI PHY channel has its own status port.
Table 24.  CPRI PHY IP Status Interface Signals for 8b/10b Interface
Signal Name Direction Width Description
o_rx_patterndetect Output 1 When asserted, indicates that the IP detects K28.5 in the current word boundary of o_rx_d and o_rx_c and the received data from RX PMA achieves word alignment. Observe with o_rx_disperr and i_rx_errdetect.
o_rx_disperr Output 2

When asserted, indicates that the received 10-bit code or data group in the current word boundary of o_rx_d and o_rx_c has a disparity error.

  • Bit 0 – status for lower data group
  • Bit 1 – status for upper data group

Causes for a disparity error include invalid data group and running disparity violations, or prior to received data group from RX PMA not yet aligned by word aligner. Invalid data group may or may not cause disparity errors depending on the data group itself and the disparities of the previous and subsequent data group. For this reason, o_rx_disperr should always be combined with o_rx_errdetect to detect all errors.

o_rx_errdetect Output 2

When asserted, indicates that a received 10-bit data group in o_rx_d or o_rx_c has an 8B/10B code violation.

  • Bit 0 – status for lower data group
  • Bit 1 – status for upper data group

Causes for a code violation include invalid data group, or earlier received data group from RX PMA not yet aligned by word aligner. To capture all errors of received data, combine this value with o_rx_disperr.

o_rx_patterndetect_x2 Output 1 When asserted, indicates that the IP detects K28.5 in the current word boundary of o_rx_d_x2 and o_rx_c_x2, and the received data from RX PMA achieves word alignment. Observe with o_rx_disperr_x2 and i_rx_errdetect_x2.
o_rx_disperr_x2 Output 4

When asserted, indicates that the received 10-bit code or data group in the current word boundary of o_rx_d_x2 and o_rx_c_x2 has a disparity error.

  • Bit 0 – status for data group [7:0]
  • Bit 1 – status for data group [15:8]
  • Bit2 – status for data group [23:16] (only for 6G/9.8G)
  • Bit3 – status for data group [31:24] (only for 6G/9.8G)

Causes for a disparity error include invalid data group and running disparity violations, or prior to received data group from RX PMA not yet aligned by word aligner. Invalid data group may or may not cause disparity errors depending on the data group itself and the disparities of the previous and subsequent data group. For this reason, o_rx_disperr_x2 should always be combined with o_rx_errdetect_x2 to detect all errors.

o_rx_errdetect_x2 Output 4

When asserted, indicates that a received 10-bit data group in o_rx_d_x2 or o_rx_c_x2 has an 8B/10B code violation.

  • Bit0 – status for data group[7:0]
  • Bit1–status for data group [15:8]
  • Bit 2 – status for data group [23:16] (only for 6G/9.8G)
  • Bit3 – status for data group [31:24] (only for 6G/9.8G)

Causes for a code violation include invalid data group, or prior to received data group from RX PMA not yet aligned by word aligner. To capture all errors of received data, this value must be combined with o_rx_disperr_x2.

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