GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 8/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

4. Functional Description

The GTS CPRI PHY Intel® FPGA IP comprises the following modules:
  • GTS transceiver channels which consists of PMA hard logic to support CPRI and Ethernet protocols. It also contains a hard PCS block that provides 64b/66b encoding scheme for 10.1376 Gbps CPRI line rate. For more information, refer to the GTS Architecture and PMA and FEC Direct PHY IP User Guide.
  • Elastic FIFO—a dual clock FIFO that matches the rate differences between the GTS hard logic and soft logic.
  • Latency measurement—a module that generates a sync pulse to measure the datapath delay of the GTS CPRI PHY Intel® FPGA IP.
  • 8b/10b PCS—a soft PCS block that provides the 8b/10b encoding scheme for the CPRI line rates of 9.8 Gbps and below.
    • IP variations with 1.2288, 2.4576, 3.072, 4.9152, 6.144, and 9.8304 Gbps CPRI line rate include a 8b/10b soft PCS.
    • IP variations that target CPRI line rates of 10.1376 Gbps use 64b/66b hard PCS within the GTS.
Figure 6. GTS CPRI PHY IP Block Diagram

Section Content
Reset Logic
Latency Measurement

Level Two Title