GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 8/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

4.2.1. Deterministic Latency

Deterministic latency is the ability to precisely determine the delay between the FPGA and the PMA pins. Such delay varies from reset to reset and device to device. In most applications, the variability is acceptable to determine the actual delay within a given reset session. This topic shows the calculation delay between pins and FPGA for the GTS CPRI PHY Intel® FPGA IP.

The deterministic latency measurement methodology for Agilex™ 5 GTS devices derives from measuring the time when a given word is present the interface to the PMA, and when that same word arrives at the FPGA. The difference in time between these two events, when added to the PMA propagation delay, determines the total latency between the FPGA and the serial pins. Such a calculation intrinsically includes all delays because of intermediate logic, FIFOs, and all other effects.
Table 10.  Deterministic Latency Factors
Factor Description
TxDL Transmitter delay in sampling clock cycle.

To calculate the TxDL value, read the CPRI PHY register 0xC bit[20:0]. The register provides the value in fixed point format. Bit[20:8] represents an unsigned integer, and bit[7:0] represents a fractional number.

For example:
  • Bit[20:8] = 0x27, the integer value is 39.
  • Bit[7:0] = 0xF4, the fractional value is 0.953125.
Therefore, the total delay is 39.953125 clock cycles.
Note: These values are available in simulation output.
RxDL Receiver delay in sampling clock cycle.

To calculate the RxDL value, read the CPRI PHY register 0x10 bit [20:0]. The register provides a value in fixed point format. Bit[20:8] represents an unsigned integer, and bit[7:0] represents a fractional number.

For example:
  • Bit[20:8] = 0x27, the integer value is 39.
  • Bit[7:0] = 0xF4, the fractional value is 0.953125.
Therefore, the total delay is 39.953125 clock cycles.
Note: These values are available in simulation output.
sampling_clock_period For GTS CPRI PHY Intel FPGA IP:
  • Sampling clock is 250 MHz.
  • Period is 4 ns.
wa Word aligner bit slip value (5 bit) obtained from GTS CPRI PHY register 0x4[9:5].
eth_wa Word aligner bit slip value (7 bit) obtained from the Datapath and PMA Avalon Memory-Mapped Interface register 0x60110[6:0].
dlpulse Obtained from the datapath and PMA Avalon Memory-Mapped Interface register (pcs_bitslip_cnt) at 0x60110 [7].
Table 11.  System Clock Frequency and Period
System Clock Frequency (MHz) system_clk_div2 period (ns)
491.52 4.06901
Table 12.  Delay Equations for 1.2G, 2.4G, 3G, 4.9G, 6G, and 9.8G Variants
Delay Equations For 1.2G, 2.4G, 3G, 4.9G, 6G, 9.8G Variants
Regular Simulation TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 229 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (347.5 + wa) * UI
Table 13.  Delay Equations for 10G without RS-FEC Variants
Delay Equations For 10G without RS-FEC Variants
Regular Simulation TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 211 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (53.5 - eth_wa - 33 * dlpulse) * UI
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