GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

3.3. Simulation

Figure 8.  Example Testbench (Duplex) for Agilex™ 5 Devices

The simulation test cases demonstrate streaming of 10,000 sample words from the traffic generator to the GTS Serial Lite IV TX core, and externally loopback to the RX core. The words are either separated into different bursts or continuously transferred in a single burst. The transfer modes are randomized by the testbench.

The simulation test case performs the following steps:
  1. Initializes and configures GTS Serial Lite IV Intel® FPGA IP, traffic generator, and traffic checker.
  2. Traffic generator generates data and starts data transmission.
  3. Logs and displays link up status and burst information.
  4. Traffic checker verifies received data and stops transmission.
  5. Testbench logs and displays test results and test information.

Section Content
Simulation Results for Basic Mode
Simulation Result for Full Mode

Level Two Title