GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

2.5. Compiling and Testing the Design

Follow these steps to compile and test the design:

  1. Launch the Quartus® Prime Pro Edition software and change the directory to example_design_dir/ed_synth/ and open the seriallite_iv_streaming_demo.qpf file.
  2. Click Processing > Start Compilation to compile the design.

    The Quartus® Prime Pro Edition software automatically loads the timing constraints for the design example and the design components during compilation.

  3. Connect the Agilex™ 5 FPGA E-Series 065B Premium Development Kit to the host computer.
  4. Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example as following:
    • systempll_ref_clk, Si5332 (U412) – OUT2: set to the value per your design requirement.
      Note: This clock is only available when the System PLL frequency selection is set to Custom and the reference frequency is different from pll_ref_clk.
    • pll_ref_clk, Si5332 (U412) – OUT0: set to the value per your design requirement.
      Note: Si5332 (U412) – OUT2 and OUT3 has to be set to the same frequency in order to be able to program.
    • iopll_ref_clk, Si5332 (U411) – OUT4: set to the value per your design requirement (which is same frequency as pll_ref_clk)
  5. In the Tools menu, click Programmer.
  6. In the Programmer, click Hardware Setup.
  7. Select a programming device.
  8. Select and add the Agilex™ 5 FPGA E-Series 065B Premium Development Kit to which your Quartus® Prime Pro Edition session can connect.
  9. Ensure that Mode is set to JTAG.
  10. Select the Agilex device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
  11. In the row with your .sof, check the box for the .sof.
  12. Check the box in the Program/Configure column and click Start.
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