GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

3.1. Features

You can use the design example to test the following features of the GTS Serial Lite IV Intel® FPGA IP:
  • Basic and full transmission modes:
    • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
    • Full mode—This is a packet transfer mode. This mode sends a burst and a sync cycle at the start and end of a packet as delimiters.
  • Transceiver data rate:
    • For NRZ mode 1 2:
      • GTS supports 1 Gbps to 16 Gbps per lane with a maximum of 4 lanes.
  • Data error reporting including PCS errors, loss of alignment, CRC errors, and data invalid errors on the RX datapath.
  • Traffic checker for data verification and lane deskew verification.
1 The maximum data rate that the IP can achieve depends on the device speed grade. Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information about maximum data rate for each device speed grade.
2 Refer to the Parameters section of the GTS Serial Lite IV Intel® FPGA IP User Guide for more details on the supported transceiver data rates for PAM4 and NRZ modes.
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