GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 813973
Date 8/05/2024
Public

3.1. Features

You can use the design example to test the following features of the GTS Serial Lite IV Intel® FPGA IP:
  • Basic and full transmission modes:
    • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
    • Full mode—This is a packet transfer mode. This mode sends a burst and a sync cycle at the start and end of a packet as delimiters.
  • Transceiver data rate:
    • For NRZ mode 1 2:
      • GTS supports 1 Gbps to 16 Gbps per lane with a maximum of 4 lanes.
  • Data error reporting including PCS errors, loss of alignment, CRC errors, and data invalid errors on the RX datapath.
  • Traffic checker for data verification and lane deskew verification.
1 The maximum data rate that the IP can achieve depends on the device speed grade. Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information about maximum data rate for each device speed grade.
2 Refer to the Parameters section of the GTS Serial Lite IV Intel® FPGA IP User Guide for more details on the supported transceiver data rates for PAM4 and NRZ modes.