GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

3.4. Hardware Testing

The hardware design example provides the loopback test. In loopback test mode, the traffic generator sends packets to the GTS Serial Lite IV TX core and loopback to the RX core either internally or externally.

Figure 9. Loopback Test

To use the system console script, navigate to the ./ed_hwtest/system_console directory. Source the sliv_gts.tcl script. The system console script provides useful commands for reading statistics and enables you to control various features in the design.

Table 9.  System Console Commands for Hardware Testing
Command Function
list_jtag Displays a list of JTAG master indexes that are connected to your board.
set_jtag <jtag master_index number> Selects the JTAG master.
  • To enable internal and external loopback, use the JTAG master index number of phy_1/phy_jtag_m JTAG node.
    For example, the JTAG master index of phy_1/phy_jtag_m JTAG node shown in the following JTAG list is 2. Type set_jtag 2 to select JTAG master index 2. Next type the enable internal or external loopback commands. 
    % list_jtag
Available JTAG Masters:
0:    /devices/<JTAG_port>/phy_0/master
1:    /devices/<JTAG_port>/phy_0/demo_jtag_m.master
2:    /device/<JTAG_port>/phy_1/phy_jtag_m.master
  • To perform commands other than internal and external loopback, use JTAG master index number of phy_0/demo_jtag_m JTAG node.
    For example, the JTAG master index of phy_0/demo_jtag_m JTAG node shown in the following JTAG list is 1. Type set_jtag 1 to select JTAG master index 1. Next type the system console command that you want to use. 
    % list_jtag
Available JTAG Masters:
0:    /devices/<JTAG_port>/phy_0/master
1:    /devices/<JTAG_port>/phy_0/demo_jtag_m.master
2:    /device/<JTAG_port>/phy_1/phy_jtag_m.master
read_error_statistic Displays the error statistics.
sl4_link_init_int_lpbk <index number> Enables TX to RX internal serial loopback within the transceiver and performs the specific transceiver calibration flow.
  • 0: Disable internal serial loopback
  • 1: Enable internal serial loopback
continuous_mode_en Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate continuous (single continuous data generation) traffic stream.
burst_mode_en

Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate a burst (multiple burst packet data generation) traffic stream.

Not applicable for Deterministic Latency Enabled design.
Figure 10. Steps to perform Hardware Testing
Figure 11. Example of Hardware Design Example Test Result in System Console
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