GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode Basic Transfer Mode Simulation Result without RS-FEC Enabled 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

3.3.1. Simulation Results for Basic Mode

The generated example testbench is dynamic and has the same configuration as the IP.

In basic or pure streaming mode, the traffic generator generates 1,000 words and transmits to the IP once the TX and RX links are established. The words are then looped back to the RX MAC. The RX MAC then sends the words to the traffic checker for data verification. In the simulation results, you can find the following information:
  • TX and RX link status
  • Configuration settings of the IP
  • Number of words transferred per burst
  • Test results with the total number of words transferred and link latency value

The following is a sample of simulation results for the design example variant without RS-FEC enabled in basic mode.

Basic Transfer Mode Simulation Result without RS-FEC Enabled

#     Waiting for Tx Link Up    
# 
#     Tx Link Up
# 
#     Waiting for Rx Link Up    
# 
#     Rx Link Up
# 
# ******** Enable PRBS Burst Mode ******** 
#     Waiting for all        1000 words to be received 
#    ******************************************* 
#     Generator Burst Count:                0    
#     Generator Words Transferred: 00000000000003e8    
#     Checker Burst Count:                  0    
#     Generator Words Received:    00000000000003e8    
#     RX Total Error:                       0    
#     RX Loss Align Error:                  0    
#     RX Data Error:                        0    
#     RX Deskew Error:                      0    
#     RX PCS Data Error:                    0    
#     RX CRC Error:                         0    
#     RX FIFO Overflow Error:               0    
#     TX FIFO Overflow Error:               0    
#     Checker Sequence Error:               0    
#     Checker Aligment Error:               0    
#     Checker Swap Error:                   0    
#    ******************************************* 
#    ******** Error Count: 0 ***************** 
#     Traffic Gen disable 
#     Tx source traffic reset  
#     Rx sink traffic reset    
#     **************************************  Test Completed  **************************************   
#     
#     Tests ended at time 194600010000
#     
#     LANES                         = 1
#     
#     Streaming Mode                = BASIC
#     
#     SRL4 Align Period             = 128
#     
#     RSFEC Enable                  = 0
#     
#     PER LANE CRC ENABLE Enable    = 0
#     
#     **************************************  Error Count: 0 ***************************************   
#     **************************************   Test Passed  **************************************** 
#     **************************************  Simulation End  **************************************
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