6. GTS JESD204C Intel® FPGA IP Parameters
Parameter | Value | Description |
---|---|---|
Main Tab | ||
Device family | Agilex™ 5 | Supports Agilex™ 5 devices. |
JESD204C wrapper |
|
Supports the JESD204C wrapper.
|
Data path |
|
Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic.
|
JESD204C Subclass |
|
Select the GTS JESD204C subclass modes.
|
Data rate |
5.0–17.16 Gbps | Set the lane rate for each lane. The maximum rate is 17.16 Gbps. Refer to Performance and Resource Utilization for more information. |
PLL/CDR reference clock frequency |
Variable | Set the transceiver reference clock frequency for PLL and CDR/PLL or CDR. The frequency range available for you to choose depends on the data rate. |
Enable dynamic reconfiguration | On | This option enables dynamic data rate change. |
Enable Native PHY Debug Master Endpoint (NPDME) | On, Off | This option enables the Transceiver Native PHY IP core to include an embedded Native PHY debug master endpoint. This endpoint connects internally to the Avalon-MM slave interface of the Transceiver Native PHY and can access the reconfiguration space of the transceiver. It can perform certain test and debug functions through JTAG using System Console. |
Enable control and status registers | On, Off | This option enables soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug. |
JESD204C Configurations Tab | ||
Lanes per converter device (L) |
1–8 | Set the number of lanes per converter device.
Note: L=3 not supported for TX.
|
Converters per device (M) |
1–32 | Set the number of converters per converter device. |
Octets per frame (F) |
1–256 | The number of octets per frame is derived from F= M*N'*S/(8*L). |
Converter resolution (N) |
1–32 | Set the number of conversion bits per converter. |
Transmitted bits per sample (N') |
4–32 | Set the number of transmitted bits per sample (JESD204 word size, which is in nibble group).
Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥ N + CS). Otherwise, parameter N' must be larger than or equal to parameter N (N'≥N).
|
Samples per converter per frame (S) |
1–32 | Set the number of transmitted samples per converter per frame. |
Multiblocks in an extended multiblock (E) |
1–32 | Set the number of multiblock within an extended multiblock. |
Control bits (CS) |
0–3 | Set the number of control bits per conversion sample. |
Control words (CF) |
0–31 | Set the number of control words per frame clock period per link. |
High-density user data format (HD) |
|
Turn on this option to set the data format. This parameter controls whether a sample may be divided over more lanes.
|
Sync header configuration (SH_CONFIG) |
|
Set the sync header (SH) encoding configuration.
|
Frame clock frequency multiplier (FCLK_MULP) |
|
Select the frame clock frequency multiplier (FCLK). The default and recommended value is 1.
|
Frame data width multiplier (WIDTH_MULP) | 1, 2, 4, 8 | Select the data width multiplier between the application layer and transport layer.
Note: The multiplier value is auto-calculated based on the M, N, S, and F configurations. Select the smallest data width multiplier value on the list. Other data width multiplier values are not allowed.
|
Enable fabric to tile TX data pipestage (Transmitter) |
|
Enable pipeline stage in TX datapath to tile for timing improvement. Turning on requires additional resources.
Note: For high data rates, Intel recommends that you enable pipeline stages for better timing.
|
TX LEMC offset (Transmitter) | 0–255 | TX LEMC offset from SYSREF. The default value is 0. |
EMB error threshold (Receiver) | 1–8 | EMB error threshold to unlock EMB FSM back to initialization state. The default value is 8. |
SH error threshold (Receiver) | 1–16 | Sync header error threshold to unlock SH FSM back to initialization state. The default value is 16. |
RX LEMC offset (Receiver) | 0–255 | RX LEMC offset from SYSREF. The default value is 0. |
RBD offset (Receiver) | 0–1023 | Elastic buffer release point (reference to LEMC) for Subclass 1 usage. The default value is 0. One full LEMC, N number means (LEMC – N) cycles to release data in elastic buffer when deskew alignment is achieved. |
Enable ECC in M20K DCFIFO (Receiver) | On, Off | Turn on to enable ECC feature if M20K is used as FIFO. |
Lane polarity attribute (Receiver) |
|
Select whether you want the lane polarity attribute to be read-only (RO) or read and write (RW).
Applies only for RX. |
Enable lane polarity detection (Receiver) | 8'h0–8'hFFFF | Specify the bit representing the polarity enable status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 7, and so on. This value depends on the number of lanes you specify. |
Polarity inversion (Receiver) | 8'h0–8'hFFFF | Specify the bit representing the polarity inversion status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 7, and so on. This value depends on the number of lanes you specify. |
Single lane mode (Receiver) | On, Off | Turn on only when you set the Sync header configuration parameter to Standalone command channel. |
Multilink mode (Receiver) | On, Off | Turn on this parameter when you want to implement synchronization between multiple GTS JESD204C RX IP instances. When you turn on this parameter, the j204c_rx_dev_emblock_align and j204c_rx_alldev_emblock_align signals are present. The IP uses the j204c_rx_dev_emblock_align and j204c_rx_alldev_emblock_align signals together with the j204c_rx_dev_lane_align and j204c_rx_alldev_lane_align signals to achieve multi-device synchronization. Refer to Receiver Signals for more information about these signals. |
Configurations and Status Registers Tab | ||
Enable CSR optimization |
On, Off | Turn on to optimize the usage of the registers, including the Avalon® memory-mapped interfaces. |