GTS JESD204C Intel® FPGA IP User Guide

ID 813959
Date 4/01/2024
Public
Document Table of Contents

4.6. Parameterizing and Generating the IP

Refer to GTS JESD204C Intel® FPGA IP Parameters for the IP parameter values and description.

  1. In the IP Catalog (Tools > IP Catalog), locate and double-click the GTS JESD204C Intel® FPGA IP.
  2. Specify a top-level name for your custom IP variation. This name identifies the IP variation files in your project. If prompted, also specify the target Intel® FPGA device family and output file HDL preference. Click OK.
  3. Click Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .ip, .qip or .qsys IP variation file and HDL files for synthesis and simulation.

    The top-level IP variation is added to the current Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Note: Some parameter options are grayed out if they are not supported in a selected configuration or it is a derived parameter.