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2.3.1. Receiver PPI Signals
2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals
2.3.3. Receiver AXI4-Stream Output Video Interface Signals
2.3.4. Receiver AXI4-Stream Output Passthrough Interface
2.3.5. Transmitter PPI Signals
2.3.6. Transmitter AXI4-Stream Input Video Interface Signals
2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
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1. About the MIPI CSI-2 Intel® FPGA IP
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
IP Version 1.2.0 |
The MIPI Camera Serial Interface 2 (MIPI CSI-2) Intel® FPGA IP is a high-speed protocol IP for transmitting video images from image sensors to application processors. This IP is compatible with the MIPI D-PHY Intel® FPGA IP.