MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues 4.3.6. Troubleshooting
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

5.1. MIPI CSI-2 Receiver

The MIPI CSI-2 receiver consists of multiple layers defined in the MIPI CSI-2 specification version 3.0, such as the lane management layer, low level protocol and byte to pixel conversion. The MIPI CSI-2 receiver receives 16-bit data per lane, with support for up to eight lanes, from the MIPI D-PHY Intel® FPGA IP through the standard PPI.
Figure 3. MIPI CSI-2 Intel® FPGA IP Receiver Block Diagram

In video mode, the low-level protocol module processes the byte data it receives on the PPI to extract the real video information. The extracted and formatted video is available on the native clocked video interface.

In passthrough mode, the low-level protocol byte stream is available directly on an AXI4-Stream interface for retransmission or custom processing.

The Clocked Video to AXI converter primarily converts the clocked video data to AXI4-Stream video data using the Intel FPGA Streaming Video Protocol. The AXI4-Stream Intel FPGA streaming video packets always follow the pattern of one (and only one) image information metapacket followed by video packets and one (and only one) end-of-field metapacket.

Each component has an Avalon® memory-mapped register interface for control and status register access and is given an address space. Bits [9:8] of the offset addresses from the system base address are 0x0 for MIPI CSI-2 RX component and 0x1 for the Clocked Video to AXI converter.
Table 22.  Top Level Interfaces
Interface Description
AXI4-Stream Intel FPGA Streaming Video (Full Variant) Carries pure video packet in Intel FPGA streaming video format. Color and byte remapped and ready for processing. Accompanied by image information packet and end of field packets. Available only when you select Video mode.
AXI4-Stream MIPI Packet AXI4-Stream interface carrying recovered MIPI CSI-2 packets. Available only when you select Passthrough mode.
PPI PHY Protocol Interface. Refer to MIPI D-PHY specification version 2.5 Annex A.
Avalon® memory-mapped interface control and status registers Control and status register.
Figure 4. MIPI CSI-2 Intel® FPGA IP Receiver (Video Mode)
Figure 5. MIPI CSI-2 Intel® FPGA IP Receiver (Passthrough Mode)
Table 23.  MIPI CSI-2 Intel® FPGA IP RX Functional Blocks
Functional Block Description
RX PPI
  • Synchronizes all D-PHY data lanes to a single clock domain (rx_word_clk_hs_d0).
  • Processes lanes de-skew if more than one data lane is in use.
  • For easier packet processing downstream, it generates start-of-packet (SOP) and end-of-packet (EOP) markers for each received packet.
Descrambling
  • Recovers the original CSI-2 data stream by reversing the CSI-2 LFSR scrambling on the video long packets.
  • Present when scrambling/descrambling is enabled when configuring the IP.
Lane Management
  • Performs lane merging function which collects incoming bytes from N number of D-PHY lanes and consolidates them into complete packets to pass on to subsequent low level protocol layers.
Error Correction Code (ECC) checking
  • Generates a new ECC for the received packet header or short packet, computes the syndrome using the new ECC and the received ECC, decodes the syndrome to find if a single bit error has occurred, and if so, corrects it.
  • If more than one bit error occurs, an uncorrectable error occurs, and an error flag is asserted in the control and status register).
Depacketizer
  • Extracts Packet Header, Packet Footer, HS-trail and all short packets.
  • Generates important markers such as start of frame (SOF), interlaced, even field or line, data type, and Virtual Channel identifier for downstream modules.
CRC and Error checking
  • Calculates the checksum of the payload data of every long packet to detect possible errors in transmission.
  • The IP compares the calculated checksum against the received 16-bit cyclic redundancy check (CRC) checksum from the packet footer. The IP flags an error for a mismatch.
  • The error detect submodule also detects frame synchronization error when a frame end (FE) is not paired with a frame start (FS) on the same virtual channel.
Byte-to-Pixel Converter
  • The video payload data from the depacketizer is unpacked based on the video data type information. The pixel output is based on the requested number of pixels in parallel.
  • An asynchronous FIFO buffer transfers the byte-based video payload data from rx_word_clk_hs_d0 clock domain to axi4s_clk clock domain. Ensure that you select axi4s_clk so that the output bandwidth is greater than the link bandwidth rather than the underlying video data rate, as the bandwidth peaks at the MIPI line rate.
Clocked Video to AXI converter
  • Converts clocked video data from the MIPI CSI-2 RX submodule to AXI4-Stream video data.
  • Resolution detection submodule retrieves the video attributes such as number of pixels per line, number of video lines per field, number of bits per symbol, color space, and interlaced or progressive at the control and status registers.
  • Stable bit is generated once video line with consistent width and height is detected. Until the input is stable, the IP produces no output video. This takes five video frames.
  • A video line buffer is present to accommodate temporary throttling on output video interface. Configure the buffer depth in the GUI to hold at least two video lines of data.
  • The scheduler ensures that the outgoing AXI4-Stream video data adheres to Intel FPGA Streaming Video (Full variant) video protocol.
Aux Output
  • Buffers the MIPI packets and transfers to axi4s_clk.
  • Present when Passthrough mode is on when generating the IP only.
Control and status Register
  • MIPI CSI-2 receiver and Clocked Video to AXI converter each have their own registers.
  • A control MUX resides at the higher layer to multiplex the control operation between both control and status registers.
  • The MSBs of the address select between accessing the MIPI CSI-2 receiver and Clocked Video to AXI converter registers.
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