MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues 4.3.6. Troubleshooting
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

5.2. MIPI CSI-2 Transmitter

The MIPI CSI-2 transmitter consists of multiple layers defined in the MIPI CSI-2 specification version 3.0, such as the pixel to byte conversion, low level protocol and lane management layer.
Figure 6. MIPI CSI-2 Intel® FPGA IP Transmitter Block Diagram

The AXI to clocked video converter receives video in the Intel FPGA Streaming Video Protocol via AXI4-Stream and converts it to clocked video format.

In video mode, the MIPI CSI-2 transmitter converts the video data into the selected CSI-2 video data type and wraps it in CSI-2 packets according to the defined low-level protocol, adding synchronization packets as required. The IP calculates long packet checksums and header ECC values to allow it to detect or correct transmission errors.

In passthrough mode, it receives MIPI CSI-2 packets on an AXI4-Stream input interface from your logic, and bypasses the video mode processing.

The IP distributes CSI-2 packets across the MIPI data lanes and to the MIPI D-PHY Intel® FPGA IP via the standard PPI.

Each component has an Avalon® memory-mapped interface register interface for control and status register access and is given an address space. Bits [9:8] of the offset addresses from the system base address are 0x0 for the MIPI CSI-2 transmitter and 0x1 for the AXI to clocked video convertor.
Table 24.  Top Level Interfaces
Interface Description
AXI4-Stream Intel FPGA Streaming Video (Full Variant) input

Carries pure video packet in Intel FPGA streaming video format. Includes image information packet and end of field packets.

Available only when you select Video mode.

AXI4_Stream MIPI Packet

AXI4-Stream input interface carrying MIPI CSI-2 packets.

Available only when you select Passthrough mode.

TX PPI PHY-Protocol Interface. Refer to MIPI D-PHY specification version 2.5 Annex A.
Avalon® memory-mapped interface control and status register Control and status register.
Figure 7. MIPI CSI-2 Intel® FPGA IP Transmitter (Video Mode)
Figure 8. MIPI CSI-2 Intel® FPGA IP Transmitter (Passthrough Mode)
Table 25.  MIPI CSI-2 Transmitter Functional Blocks
Functional Block Description
AXI to clocked video converter
  • Receives AXI4-Stream Intel Video Streaming Protocol (full variant) data and converts to clocked video data for the MIPI CSI-2 transmitter.
  • Generates synchronization short packets for insertion into the CSI-2 data stream around the video packets
  • Supports multiple channels – arbitrates between input channels in round-robin order. The IP uses the channel number to set the virtual channel ID in the MIPI CSI-2 data stream.
Pixel-to-byte converter
  • Converts the video data from pixel format to the selected MIPI CSI-2 data type as defined in the CSI-2 specification.
  • Packs pixel data into bus with width that ensures that the MIPI link is fully occupied.
Packet arbiter Multiplexes synchronization short packets, video long packets and generic short packets into a single stream.
Error Correction Code (ECC) Calculates the ECC for each packet header.
Packetizer
  • Applies long packet header.
  • Long packet payload CRC is calculated and appended after payload.
Lane distributor Distributes the bytes from the incoming packet stream onto the configured number of MIPI lanes according to the CSI-2 specification.
Scrambler When configured this applies the CSI-2 linear feedback shift register (LFSR) scrambling function to long packet payloads to avoid any long periods of fixed signaling when the video data is constant.
PPI Performs handshaking with D-PHY IP to transmit CSI-2 packets.
Control and status register
  • MIPI CSI-2 transmitter and AXI to clocked video converter submodules each have their own CSRs.
  • A control MUX resides at the higher layer to multiplex the control operation between both control and status registers.
  • The MSBs of the address select between accessing the MIPI CSI-2 transmitter and AXI to clocked video converter control and status registers.
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