MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues 4.3.6. Troubleshooting
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

4.3.6. Troubleshooting

In most instances the MIPI CSI-2 IP does not require active monitoring. If the video transfer is unreliable, you can try various steps to isolate the problem. Initially confirm that the build-time configuration of the MIPI D-PHY and MIPI CSI-2 IPs match those configured in your external MIPI source or sink. Also check that the Quartus Prime project pin assignments correlate with the PCB layout.

The CSI-2 IP passes no video until it receives five consecutive video frames with constant dimensions, which reduces the likelihood the IP produces corrupted video data. If the video input is unstable, you see no video output.

  1. For the receiver:
    1. Read the error IRQ status registers in the CSI-2 IP to determine whether the IP detected any errors on the incoming video stream.
    2. Check the CSI-2 IP VCx_VIDEO_DATA_TYPE registers record the most recent video data type received on each virtual channel. The registers show that video packets arriving at the CSI-2 input are of the expected data type and that the virtual channel ID in the video packets is correct. Registers reading zero, indicate the IP received no valid video packets on this channel.
    3. Check the VIDEO_INTFx_WIDTH/HEIGHT/COLOR_PATTERN registers in the CSI-2 IP record the most recent video data characteristics received from the MIPI source. If these registers fluctuate, check for a signal integrity issue on the MIPI transmission line to the FPGA. If these regsiters are incorrect but constant, check the configuration of the MIPI source.
    4. Check the VIDEO_INTFx_STABLE register indicates that video data on each channel remains active and has constant dimensions. Dimensions available in the registers above but with no stable flag indicate an unreliable input to the FPGA.
    5. Ensure that the AXI-S video streaming output from the CSI-2 IP can flow adequately, as you cannot use backpressure at the MIPI video input. If insufficient flow is available, receive buffers within the CSI-2 IP overflow and the PIP loses or corrupts data.
      • Monitor data flow with the Signal Tap logic analyzer and ensure sufficient bandwidth in general, by comparing the video line rate on the PPI between the D-PHY and CSI-2 IPs with that on the output of the CSI-2 IP. A lower CSI-2 line rate indicates insufficient flow.
      • To confirm, tie the output video AXI-S TREADY signals to logic ‘1’ and observe to see if the problem is resolved. If the problem is resolved, the system architecture does not support the required bandwidth. Select a higher number of pixels-in-parallel on the CSI-2 video output to increase the bandwidth (and update the downstream logic). Alternatively, change the downstream logic to reduce cycles where TREADY is not asserted to improve throughput.
  2. For the transmitter:
    1. Confirm that the video parameters are correct in the VIDEO_INTFx_WIDTH/HEIGHT/COLOR_PATTERN and VCx_LINE-BLANK/FRAME_BLANK registers in the CSI-2 IP.
    2. Check that the VCx_MODE_MATCH registers in the CSI-2 IP indicate that the incoming video dimensions match the configured values.
    3. Ensure that video flow into the IP is sufficient to provide enough video data to drive the output at the rate configured. If video data is not available to send at the configured line or frame interval, the IP skips video packets.
    4. Check error status in the MIPI sink in your system. Errors may indicate signal integrity issues.
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