Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 9/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives 7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features 1.2. Agilex™ 5 Embedded Memory Block Signals
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 5 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Configuration Methods 4.2.3. Specifications 4.2.4. FIFO Functional Timing Requirements 4.2.5. SCFIFO ALMOST_EMPTY Functional Timing 4.2.6. FIFO Output Status Flag and Latency 4.2.7. FIFO Metastability Protection and Related Options 4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.9. SCFIFO and DCFIFO Show-Ahead Mode 4.2.10. Different Input and Output Width 4.2.11. DCFIFO Timing Constraint Setting 4.2.12. Coding Example for Manual Instantiation 4.2.13. Instantiation Template 4.2.14. Design Example 4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.16. Guidelines for Embedded Memory ECC Feature 4.2.17. FIFO Intel® FPGA IP Parameters 4.2.18. Reset Scheme
4.2.3. Specifications x
4.2.3.1. Verilog HDL Prototype 4.2.3.2. VHDL Component Declaration 4.2.3.3. VHDL LIBRARY-USE Declaration 4.2.3.4. HDL Code from Parameterizable Macros Template 4.2.3.5. FIFO Signals 4.2.3.6. FIFO Parameter Settings
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.11. DCFIFO Timing Constraint Setting x
4.2.11.1. Embedded Timing Constraint 4.2.11.2. User Configurable Timing Constraint
4.2.11.2. User Configurable Timing Constraint x
4.2.11.2.1. SDC Commands
4.3. Shift Register (RAM-based) Intel® FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.3.5. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

4.1.7.1. RAM and ROM Parameter Settings

Table 29.   Parameters for altera_syncram Use the parameter list when editing the design file manually.
Name Legal Values Description
operation_mode

SINGLE_PORT

DUAL_PORT

BIDIR_DUAL_PORT

QUAD_PORT

ROM

Operation mode of the memory block.
width_a — Data width of port A.
widthad_a — Address width of port A.
numwords_a — Number of data words in the memory block for port A.
outdata_reg_a

UNREGISTERED

CLOCK1

CLOCK0

Clock for the data output registers of port A.
outdata_aclr_a

NONE

CLEAR1

CLEAR0

Asynchronous clear for data output registers of port A. When the outdata_reg_a parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
address_aclr_a

NONE

CLEAR0 		Option to clear the address input registers of port A.
width_byteena_a — Width of the byte-enable bus of port A. The width must be equal to the value of width_a divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
width_b — Data width of port B.
widthad_b — Address width of port B.
numwords_b — Number of data words in the memory block for port B.
outdata_reg_b

UNREGISTERED

CLOCK1

CLOCK0

Clock for the data output registers of port B.
address_reg_b

CLOCK1

CLOCK0

Clock for the address registers of port B.
outdata_aclr_b

NONE

CLEAR1

CLEAR0

Asynchronous clear for data output registers of port B. When the outdata_reg_b parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
address_aclr_b

NONE

CLEAR0 		Option to clear the address input registers of port B.
width_byteena_b — Width of the byte-enable bus of port B. The width must be equal to the value of width_b divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
intended_device_family

“Agilex”

Parameter used for simulation purpose.
ram_block_type

AUTO

M20K

MLAB

The memory block type.
byte_size

5

8

9

10

The byte size for the byte-enable mode.
read_during_write_mode_mixed_ports

DONT_CARE

CONSTRAINT_DONT_CARE

NEW_DATA

OLD_DATA

NEW_A_OLD_B

The behavior for the read-during-write mode.
  • The default value is DONT_CARE.
  • The value of NEW_DATA is supported only when the read address and output data are registered by the write clock in the LUTRAM mode or when true dual port mode is selected for M20K.
  • The value of CONSTRAINED_DONT_CARE is supported only in the LUTRAM mode.
  • The value of NEW_A_OLD_B is supported only when the operation_mode parameter is set to QUAD_PORT.
init_file

*.mif

*.hex

The initialization file.
init_file_layout

PORT_A

PORT_B 		The layout of the initialization file.
maximum_depth — The depth of the memory block slices.
clock_enable_input_a

NORMAL

BYPASS

The clock enable for the input registers of port A.
clock_enable_output_a

NORMAL

BYPASS

The clock enable for the output registers of port A.
clock_enable_input_b

NORMAL

BYPASS

The clock enable for the input registers of port B.
clock_enable_output_b

NORMAL

BYPASS

The clock enable for the output registers of port B.
read_during_write_mode_port_a

NEW_DATA_NO_NBE_READ

NEW_DATA_WITH_NBE_READ

OLD_DATA

DONT_CARE

The read-during-write behavior for port A.
read_during_write_mode_port_b

NEW_DATA_NO_NBE_READ

NEW_DATA_WITH_NBE_READ

OLD_DATA

DONT_CARE

The read-during-write behavior for port B.
enable_ecc

TRUE

FALSE

Enables or disables the ECC feature.
ecc_pipeline_stage_enabled

TRUE

FALSE

  • Specifies whether to enable ECC Pipeline Registers before the output decoder to achieve the same performance as non-ECC mode at the expense of one cycle of latency.
  • The parameter enable_ecc must set to TRUE if this parameter is set to TRUE.
  • The parameter outdata_reg_b cannot set to UNREGISTERED if this parameter is set to TRUE.
  • The default value is FALSE.
enable_ecc_encoder_bypass

TRUE

FALSE

Enables or disables the ECC Encoder Bypass feature.
  • The parameter enable_ecc must set to TRUE if this parameter is set to TRUE.
enable_coherent_read

TRUE

FALSE

Enables or disables the coherent read feature.
  • The default value is FALSE.
enable_force_to_zero

TRUE

FALSE

Enables or disables the Force-to-Zero feature.
  • The default value is FALSE.
optimization_option

AUTO

HIGH_SPEED

LOW_POWER

Specifies how the RAM block would be optimized.
  • If AUTO is selected, the fitter determines whether the RAM block is in High_Speed or Low_Power mode.
  • The RAM block type must be M20K when High_Speed or Low_Power is selected.
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