Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives 7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features 1.2. Agilex™ 5 Embedded Memory Block Signals
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 5 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Configuration Methods 4.2.3. Specifications 4.2.4. FIFO Functional Timing Requirements 4.2.5. SCFIFO ALMOST_EMPTY Functional Timing 4.2.6. FIFO Output Status Flag and Latency 4.2.7. FIFO Metastability Protection and Related Options 4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.9. SCFIFO and DCFIFO Show-Ahead Mode 4.2.10. Different Input and Output Width 4.2.11. DCFIFO Timing Constraint Setting 4.2.12. Coding Example for Manual Instantiation 4.2.13. Instantiation Template 4.2.14. Design Example 4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.16. Guidelines for Embedded Memory ECC Feature 4.2.17. FIFO Intel® FPGA IP Parameters 4.2.18. Reset Scheme
4.2.3. Specifications x
4.2.3.1. Verilog HDL Prototype 4.2.3.2. VHDL Component Declaration 4.2.3.3. VHDL LIBRARY-USE Declaration 4.2.3.4. HDL Code from Parameterizable Macros Template 4.2.3.5. FIFO Signals 4.2.3.6. FIFO Parameter Settings
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.11. DCFIFO Timing Constraint Setting x
4.2.11.1. Embedded Timing Constraint 4.2.11.2. User Configurable Timing Constraint
4.2.11.2. User Configurable Timing Constraint x
4.2.11.2.1. SDC Commands
4.3. Shift Register (RAM-based) Intel® FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.3.5. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

4.2.6. FIFO Output Status Flag and Latency

The main concern in most FIFO design is the output latency of the read and write status signals.
Table 36.  Output Latency of the Status Flags for SCFIFOThis table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the SCFIFO according to the different output modes and optimization options.
Output Mode Optimization Option 17 Output Latency (in number of clock cycles)
Normal 18 Speed wrreq / rdreq to full: 1
wrreq to empty: 2
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq / rdreq to empty : 1
wrreq / rdreq to usedw[] : 1
rdreq to q[]: 1
Show-ahead 18 Speed wrreq / rdreq to full: 1
wrreq to empty: 3
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 3
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq to empty: 2
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 2
rdreq to q[]: 1
Table 37.  ALM Implemented RAM Mode for SCFIFO and DCFIFO
Output Mode Optimization Option 19 Output Latency (in number of clock cycles)
Normal 20 Speed wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq / rdreq to empty : 1
wrreq / rdreq to usedw[] : 1
rdreq to q[]: 1
Show-ahead 20 Speed wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 1
rdreq to q[]: 1
Table 38.  Output Latency of the Status Flag for the DCFIFO This table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the DCFIFO.
Output Latency (in number of clock cycles)
wrreq to wrfull: 1 wrclk
wrreq to rdfull: 2 wrclk cycles + following n rdclk 21
wrreq to wrempty: 1 wrclk
wrreq to rdempty: 2 wrclk 22 + following n rdclk 22
wrreq to wrusedw[]: 2 wrclk
wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 22
wrreq to q[]: 1 wrclk + following 1 rdclk 22
rdreq to rdempty: 1 rdclk
rdreq to wrempty: 1 rdclk + following n wrclk 22
rdreq to rfull: 1 rdclk
rdreq to wrfull: 1 rdclk + following n wrclk 22
rdreq to rdusedw[]: 2 rdclk
rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 22
rdreq to q[]: 1 rdclk
17 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
18 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
19 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
20 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
21 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options .
22 This is applied only to Show-ahead output modes. Show-ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON.
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