Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Agilex™ 5 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Configuration Methods 4.2.3. Specifications 4.2.4. FIFO Functional Timing Requirements 4.2.5. SCFIFO ALMOST_EMPTY Functional Timing 4.2.6. FIFO Output Status Flag and Latency 4.2.7. FIFO Metastability Protection and Related Options 4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.9. SCFIFO and DCFIFO Show-Ahead Mode 4.2.10. Different Input and Output Width 4.2.11. DCFIFO Timing Constraint Setting 4.2.12. Coding Example for Manual Instantiation 4.2.13. Instantiation Template 4.2.14. Design Example 4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.16. Guidelines for Embedded Memory ECC Feature 4.2.17. FIFO Intel® FPGA IP Parameters 4.2.18. Reset Scheme
4.2.3. Specifications x
4.2.3.1. Verilog HDL Prototype 4.2.3.2. VHDL Component Declaration 4.2.3.3. VHDL LIBRARY-USE Declaration 4.2.3.4. HDL Code from Parameterizable Macros Template 4.2.3.5. FIFO Signals 4.2.3.6. FIFO Parameter Settings
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.11. DCFIFO Timing Constraint Setting x
4.2.11.1. Embedded Timing Constraint 4.2.11.2. User Configurable Timing Constraint
4.2.11.2. User Configurable Timing Constraint x
4.2.11.2.1. SDC Commands
4.3. Shift Register (RAM-based) Intel® FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.3.5. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

4.2.3.6. FIFO Parameter Settings

Table 31.  FIFO Parameters
Parameter Type Required Description

DATA_WIDTH 10

DATA_WIDTH_A 11

Integer Yes

For SCFIFO, it specifies the width of the data and q ports. For DCFIFO, it specifies the width of the data port only.

DATA_WIDTH_B 11 Integer Yes

Specifies the width of the q port for the DCFIFO_MIXED_WIDTHS FIFO macro. (If similar port data is used, give value as DATA_WIDTH_B = DATA_WIDTH_A)

ADDR_WIDTH 10

ADDR_WIDTH_A 11

Integer Yes Specifies the width of the usedw port for the SCFIFO function, or the width of the rdusedw and wrusedw ports for the DCFIFO function. For the DCFIFO_MIXED_WIDTHS function, it only represents the width of the wrusedw port.
ADDR_WIDTH_B 11 Integer Yes Specifies the width of the rdusedw port for the DCFIFO_MIXED_WIDTHS function.

(If similar port data is used, give value as DATA_WIDTH_B = DATA_WIDTH_A

ENABLE_ACLR 10 String No Specifies whether to set ENABLE_ACLR parameter ON or OFF. Asynchronous clear choice for data output of FIFO.
ENABLE_SCLR 10 String No Specifies whether to ENABLE_SCLR parameter ON or OFF. Synchronous clear choice for data output of FIFO.
MAXIMUM_DEPTH Integer Yes Maximum depth. You can set the preferred maximum depth with MAXIMUM_DEPTH=<depth>. The value assigned must comply with the following equation:
  • For SCFIFO: 2^ADDR_WIDTH
  • For DCFIFO: 2^ADDR_WIDTH_A or 2^ADDR_WIDTH_B
ENABLE_SHOWAHEAD String Yes Specifies whether the FIFO is in normal mode (OFF) or show-ahead mode (ON). For more details, refer to SCFIFO and DCFIFO Look-Ahead Mode section.

If you set the parameter to ON, you may reduce performance.

OVERFLOW_CHECKING String No Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO Intel® FPGA IP core is full. The values are ON or OFF. If omitted, the default is ON.
UNDERFLOW_CHECKING String No Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq port when the FIFO Intel® FPGA IP core is empty. The values are ON or OFF. If omitted, the default is ON.

Note that reading from an empty SCFIFO gives unpredictable results.
ADD_USEDW_MSB_BIT 11 String No Increases the width of the rdusedw and wrusedw ports by one bit. By increasing the width, it prevents the FIFO Intel® FPGA IP core from rolling over to zero when it is full. The values are ON or OFF. If omitted, the default value is OFF.
RDSYNC_DELAYPIPE 11

WRSYNC_DELAYPIPE 11

Integer No Specify the number of synchronization stages in the cross clock domain. The value of the rdsync_delaypipe parameter relates the synchronization stages from the write control logic to the read control logic; the wrsync_delaypipe parameter relates the synchronization stages from the read control logic to the write control logic.
WRITE_ACLR_SYNCH 11 String No Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the wrclk clock. Adding the circuit prevents the race condition between the wrreq and aclr ports that could corrupt the FIFO Intel® FPGA IP core.

The values are ON or OFF. If omitted, the default value is OFF.

READ_ACLR_SYNCH 11 String No Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the rdclk clock. Adding the circuit prevents the race condition between the rdreq and aclr ports that could corrupt the FIFO Intel® FPGA IP core.

The values are ON or OFF. If omitted, the default value is OFF.

RAM_BLOCK_TYPE String No

Specifies the target device’s Memory Block to be used: “Auto”, “MLAB”, “M20K”.
ADD_RAM_OUTPUT_REGISTER 11 String No Specifies whether to register the q output. The values are ON and OFF. If omitted, the default value is OFF.
ALMOST_FULL_VALUE 10 Integer No Sets the threshold value for the almost_full port. When the number of words stored in the FIFO is greater than or equal to this value, the almost_full port is asserted.
ALMOST_EMPTY_VALUE 10 Integer No Sets the threshold value for the almost_empty port. When the number of words stored in the FIFO Intel® FPGA IP core is less than this value, the almost_empty port is asserted.
ALLOW_WRCYCLE_WHEN_FULL 10 String No Allows you to combine read and write cycles to an already full SCFIFO, so that it remains full. The values are ON and OFF. If omitted, the default is OFF. Use only this parameter when the OVERFLOW_CHECKING parameter is set to ON.
BYTE_SIZE Integer Yes Specifies the size of the byte for byteenable mode.
BYTE_EN_WIDTH Integer Yes Width of the byte enable bus at Port A. This width should be equal to DATA_WIDTH (SCFIFO) or DATA_WIDTH_A (DCFIFO) divided by BYTE_SIZE.
10 Only applicable for the SCFIFO function.
11 Only applicable for the DCFIFO function.
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