Visible to Intel only — GUID: eis1414476362210
Ixiasoft
Visible to Intel only — GUID: eis1414476362210
Ixiasoft
4.2.11.1. Embedded Timing Constraint
- For paths crossing from the write into the read domain, apply a false path assignment between the delayed_wrptr_g and rs_dgwp registers:
set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
- For paths crossing from the read into the write domain, apply a false path assignment between the rdptr_g and ws_dgrp registers:
set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
The false path assignments are automatically added through the HDL-embedded Synopsis design constraint (SDC) commands when you compile your design. The related message is shown under the Timing Analyzer report.
If you use the Quartus® Prime Timing Analyzer, the false paths are applied automatically for the DCFIFO.