Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock and Reset Signals
2.2.4. Simulation x
2.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.2.5.1. Test Procedure

After you compile the Triple-Speed Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 5 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

Note: You must connect the external loopback module to the QSFP28 port on bank 1A before running the test.
  1. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest/agx/2xtbi_pma to change directory to <design_example_dir>/hardware_test_design/hwtest/agx/2xtbi_pma.
  3. Type source basic/basic.tcl.
  4. Type list_jtag to display a list of JTAG master indexes that are connected to your board.
  5. Type set_jtag<number_of appropriate_JTAG_master> to select the JTAG master.
  6. Type source hwtest_main.tcl to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message:
Level Two Title