Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock and Reset Signals
2.2.4. Simulation x
2.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.1.1. Directory Structure

The Triple-Speed Ethernet Intel® FPGA IP design example file directories contain the following generated files:

  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only design example is located in <design_example_dir>/compilation_test_design.
  • The compilation test and hardware test designs use files in <design_example_dir>/ex_tse/common.
Figure 10. Directory Structure for the Design Example
Table 7.  Testbench File Description
Directory/File Description
Testbench and Simulation Files
<design_example_dir>/example_testbench/basic_avl_tb_top_mac_pcs.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/ basic_avl_tb_top_mac_pcs_msim.sv Top-level testbench file for QuestaSim* and Riviera-PRO* simulation. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/ basic_avl_tb_top_mac_pcs_nc.sv Top-level testbench file for Xcelium* simulation. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
<design_example_dir>/example_testbench/ run_vsim_mac_pcs.sh The QuestaSim* script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx_mac_pcs.sh The Synopsys* VCS MX script to run the testbench
<design_example_dir>/example_testbench/run_xcelium_mac_pcs.sh The Xcelium* script to run the testbench.
<design_example_dir>/example_testbench/ run_rivierapro_mac_pcs.do The Riviera-PRO* script to run the testbench.
Table 8.  Hardware Design Example File Description
Directory/File Description

<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.qpf

Quartus® Prime project file.

<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.qsf

Quartus® Prime project settings file.

<design_example_dir>/hardware_test_design/intel_eth_tse_hw.sdc

Synopsys* Design Constraints files. You can copy and modify these files for your own design.

<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.v

Top-level Verilog HDL design example file.

<design_example_dir>/hardware_test_design/common/

Hardware design example support files.
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