Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock and Reset Signals
2.2.4. Simulation x
2.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2024.10.07 24.3 6.0.0 Added a new design example variant: 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS).
2024.07.08 24.2 5.0.0
  • Updated the description in the Quick Start Guide topic.
  • Updated Development Stages for the Design Example figure.
  • Added a note about the Agilex™ 5 D-Series FPGAs and SoCs support in the Quick Start Guide topic.
  • Updated Directory Structure for the Design Example figure.
  • Updated Testbench File Description table.
  • Updated Generating the Design Example topic to include the steps to select the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) target development kit.
  • Updated Parameters in the Example Design Tab table.
  • Removed VCS* from Steps to Simulate the Testbench table.
  • Added Compiling and Configuring the Design Example in Hardware topic.
  • Updated the following for 10/100/1000 ethernet MAC design example with 1000BASE-X/SGMII 2XTBI PCS with GTS transceiver:
    • Features topic.
    • Hardware and Software Requirements topic.
    • Block Diagram—10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver.
    • Updated PCS/Transceiver Options in the Design Components table.
    • Updated Block Diagram of the 10/100/1000Mb Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver Simulation Testbench figure.
    • Added Hardware Testing, Test Procedure topic.
  • Updated description for pll_refclk0 and reg_clk signals in the Interface Signals for 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver table.
2024.04.01 24.1 4.0.0 Initial release.
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