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1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. HPS EMIF Platform Designer Example Designs
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
5.1. Terminology
5.2. Block Diagram
5.3. Version Support
5.4. Download Example Design Files
5.5. HPS EMIF Platform Designer Example Designs
5.6. Specific Examples
5.7. General Connection Guideline
5.8. Supported Memory Protocols Differences Among Intel SoC Device Families
5.9. IO96 Bank and Lane Usage for HPS EMIF
5.10. Quartus Report of I/O Bank Usage
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3.2.3.2. Steps to run the Simulation in Synopsys* VCS*
- In agilex5_hps_f2h_simulation_tb/agilex5_hps_f2h_simulation_tb/sim/synopsys/vcs/vcs_setup.sh, modify the “QUARTUS_INSTALL_DIR” to point to the correct Quartus® Prime installation path. (This step is not required if your design is generated per RTL Simulation Setup Scripts).
- In the top directory, launch the VCS* simulator with command:
bash vcs_run.sh 64
The standard output from the VCS* test and simulation process is printed out on the terminal. - To view the signal waveforms, navigate to the VCS* directory:
cd agilex5_hps_f2h_simulation_tb/ \ agilex5_hps_f2h_simulation_tb/sim/synopsys/vcs
- Launch the VCS* GUI using the command:
simv -gui &
- In the GUI window, you may add in waveform signals by selecting right-click on the signal group, and choosing Add to Waves > New Wave View.
Figure 58. New Wave View
- A new Waveform View window is launched. From the window, click on the “Start/Continue” button or press “F5” key to run the waveform simulation.
Figure 59. New Waveform View window
- When the simulation is completed, you can zoom in to view the waveform of each signal.
Figure 60. Waveform View (Zoom In)