Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.3.2. Reset Signals

Figure 21.  Platform Designer Reset Signals Sub-window
This section contains the Agilex™ 5 HPS reset signals configuration.
  • Turning on the Enable HPS Warm Reset handshake signals option enables an additional pair of reset handshake signals allowing soft logic to notify the HPS when it is safe to initiate a warm reset in the FPGA fabric. Turning on this option exposes the h2f_warm_reset_handshake conduit, which is comprised of the signals h2f_warm_reset_handshake_reset_req and h2f_warm_reset_handshake_reset_ack.
  • Turning on the Enable HPS-to-FPGA Cold Reset output option exposes the h2f_cold_reset reset output interface. This signal is asserted when the HPS undergoes a cold reset.
  • Turning on the Enable Watchdog Reset option exposes the h2f_watchdog_reset reset output interface and is asserted when the HPS watchdog timers are triggered.
  • Watchdog SDM Configuration dropdown provides an input to the compiled bitstream that directs the SDM to treat the HPS watchdog reset assertion as an HPS Cold Reset, HPS Warm Reset, or Trigger Remote Update.

For more information, refer to the HPS System Reset Considerations chapter in the Design Guidelines section.