Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC

Figure 25. Selection GUI for NAND, SDMMC, TRACE, TPIU, EMAC
  • Bit-width Options: This dropdown option is only enabled if the NAND, SD/MMC, or TRACE peripherals are enabled. This option is to specify the desired bit-width of the interface routed to the HPS I/O or FPGA.
  • TPIU Clock Source: TPIU Clock Source allows you to select whether the Trace input clock comes internally from HPS Clock Manager or from and external clock input FPGA Trace Clock. This option is only enabled if Trace peripheral IP is used on FPGA or HPS I/O.
  • EMAC Options: If any of the EMACs are enabled, the corresponding Interface, PHY Options, and PPS Enable dropdowns become available to specify the desired EMAC A to C parameters.

    EMAC options are mapped to HPS EMAC first, followed by FPGA EMAC. For example, if two EMACs are enabled on HPS and one EMAC is enabled on FPGA. EMAC A and EMAC B options are mapped to EMAC0 and EMAC1 on HPS IO. Alternatively, it could also be EMAC1 and EMAC2 or EMAC0 and EMAC2 respectively. You can expect EMAC C options to then map to the single EMAC on FPGA which would be the EMAC number that is not used by HPS IO (in the first case this would be EMAC2 to FPGA).

  • EMAC Interface Options: You can expect the EMAC Interface options to reflect two available modes for each EMAC:
    • For EMACs on HPS I/O—RGMII which corresponds to data widths of four or two respectively.
    • For EMACs on FPGA—GMII corresponding to data widths of eight or four respectively.
  • EMAC PHY Options: The EMAC PHY Options can be used to enable additional PHY interfaces for the EMAC and include a selection of MDIO or I2C. Either options are expected to add the corresponding EMAC MDIO or I2C phy ports to FPGA or HPS I/O respectively.
  • EMAC PPS Enable:

    The EMAC PPS Enable option is only available for EMACs on the HPS I/O and indicates that the respective EMAC interface is expected to include placement of the PPS and PPSTRIG signals.