Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.2.2. FPGA to SDRAM Subordinate

The FPGA-to-SDRAM 256-/128-/64-bit AXI* 4 interface enables access from the FPGA to SDRAM for non-coherent transactions. If the FPGA-to-SDRAM is used, then the spare IOs on the IO Bank are not available for use.

For more information, refer to the MPFE and MPFE-lite chapter in the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.

  • Enable/Data Width drop-down to configure this manager interface's data widths
    • Unused
    • 256-bit
    • 128-bit
    • 64-bit
  • Interface Address Width is configurable from 40 bits down to 20 bits.
When this bridge is enabled, the interfaces: f2sdram, f2sdram_axi_clock, and f2sdram_axi_reset are made available.
Note: h2f_reset signal must be connected to f2sdram_axi_reset signal for proper bridge operation.