Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

3.5. FPGA-to-SDRAM AXI* Subordinate Interface

The FPGA-to-SDRAM AXI* subordinate interface, f2sdram, is connected to a Mentor Graphics* AXI* 4 subordinate BFM for simulation with an instance name of f2sdram_axi4_subordinate_inst. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to the f2sdram_axi_clock clock.

Table 19.  Configuration of FPGA-to-SDRAM AXI* Subordinate BFM
Parameter Value
AXI* Address Width 20-40
AXI* Read Data Width 64, 128 or 256
AXI* Write Data Width 64, 128 or 256
AXI* ID Width 5