Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.2.1. FPGA to HPS Subordinate

FPGA-to-HPS subordinate interface allow the FPGA manager to issue transactions to the HPS.

  • Interface Specification drop-down to configure this manager interface:
    • AXI* 4
    • ACE-Lite
    • AXI* 5
  • Enable/Data Width drop-down to configure this manager interface's data widths
    • Unused
    • 256-bit
  • Interface Address Width is configurable from 40 bits down to 20 bits, which allows the FPGA fabric to access the majority of the HPS address space. To facilitate initiators in the FPGA logic with a smaller address width than the bridge in accessing the HPS address space, you can use the Intel Address Span Extender component.
  • Enable System MMU option enables the SMMU (TBU) feature on the FPGA-to-HPS path. This feature supports virtual addressing of the DDR/HPS. The SMMU ports are enabled and exposed as extended ARUSER and AWUSER port at top-level.
When this bridge is enabled, the interfaces: fpga2hps, fpga2hps_clock, and fpga2hps_reset are made available.
Note: The h2f_reset signal must be connected to the fpga2hps_reset signal for proper bridge operation.