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1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. HPS EMIF Platform Designer Example Designs
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
5.1. Terminology
5.2. Block Diagram
5.3. Version Support
5.4. Download Example Design Files
5.5. HPS EMIF Platform Designer Example Designs
5.6. Specific Examples
5.7. General Connection Guideline
5.8. Supported Memory Protocols Differences Among Intel SoC Device Families
5.9. IO96 Bank and Lane Usage for HPS EMIF
5.10. Quartus Report of I/O Bank Usage
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2.2.2.1. FPGA to HPS Subordinate
FPGA-to-HPS subordinate interface allow the FPGA manager to issue transactions to the HPS.
- Interface Specification drop-down to configure this manager interface:
- AXI* 4
- ACE-Lite
- AXI* 5
- Enable/Data Width drop-down to configure this manager interface's data widths
- Unused
- 256-bit
- Interface Address Width is configurable from 40 bits down to 20 bits, which allows the FPGA fabric to access the majority of the HPS address space. To facilitate initiators in the FPGA logic with a smaller address width than the bridge in accessing the HPS address space, you can use the Intel Address Span Extender component.
- Enable System MMU option enables the SMMU (TBU) feature on the FPGA-to-HPS path. This feature supports virtual addressing of the DDR/HPS. The SMMU ports are enabled and exposed as extended ARUSER and AWUSER port at top-level.
When this bridge is enabled, the interfaces: fpga2hps, fpga2hps_clock, and fpga2hps_reset are made available.
Note: The h2f_reset signal must be connected to the fpga2hps_reset signal for proper bridge operation.