Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

3.1.3.2. Cadence® Xcelium* Simulation Steps

  1. Locate your top-level simulation model.
    1. You can locate it at <project directory>/<Platform Designer design name>/sim/.
    2. Use the name located from the previous step (step a) to replace the placeholder names TopLevel.v and TopLevel that are used in the following steps.
  2. Locate the Cadence® setup script.
    1. You can locate it at <project directory>/<Platform Designer design name>/sim/xcelium/.
    2. Locate xcelium_setup.sh.
  3. For this example, the simulator is executed in the sim/xcelium directory where the vcs_setup.sh file is located. Change directory to the sim/xcelium directory:
    cd <project directory>/<Platform Designer design name>/ \
    sim/xcelium/
  4. Copy the xcelium_setup.sh file to another file. For this exercise, it is called my_xmsim_script.sh.
    cp xcelium_setup.sh my_xmsim_script.sh
  5. In your my_xmsim_script.sh file, delete everything except the section between the lines from "TOP-LEVEL TEMPLATE - BEGIN" to "TOP-LEVEL TEMPLATE - END".
  6. In your my_xmsim_script.sh file, add additional libraries and flags by adding the following lines at the top of the file:
    MVCHOME=<ACDS directory>/ip/altera/mentor_vip_ae/common/
    RUN_64bit=-64bit
    QUESTA_MVC_GCC_LIB=${MVCHOME}/questa_mvc_core/linux_x86_64_gcc-6.3_ius
    export LD_LIBRARY_PATH=${QUESTA_MVC_GCC_LIB}:${LD_LIBRARY_PATH}
    
    
  7. Uncomment the first set of lines that source xcelium_setup.sh in the template and modify to the following:
    source xcelium_setup.sh \
    SKIP_ELAB=1 \
    SKIP_SIM=1
    
  8. Uncomment and modify the "xmvlog" line in the template:
    xmvlog ../TopLevel.v
  9. Uncomment the second set of lines that source xcelium_setup.sh in the template and modify to the following:
    source xcelium_setup.sh \
    SKIP_FILE_COPY=1 \
    SKIP_DEV_COM=1 \
    SKIP_COM=1 \
    TOP_LEVEL_NAME=TopLevel \
    USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ns\ -no_mixed_bus\ \ 
    -ENABLE_BIND_WITH_COMMON_PKG" \
    USER_DEFINED_SIM_OPTIONS="-sv_root\ ${QUESTA_MVC_GCC_LIB}\ -sv_lib\ \ 
    libaxi4_IN_SystemVerilog_IUS_full_DVC"
    
  10. Save the my_xmsim_script.sh file.
  11. Setup your developer environment with the proper resources. Refer to Cadence® Xcelium* documentation for downloading, installing, and licensing.
  12. Run the simulation script:
    sh my_xmsim_script.sh
  13. The simulation is running without any errors. Since no testbench is added, it only shows that all the HPS IP simulation files were successfully compiled and elaborated.