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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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6.1. Register Map
Word Offset | Purpose | Variation |
---|---|---|
0x0000: 0x000F | Reserved | — |
0x0010: 0x0011 | Primary MAC Address | MAC TX, MAC RX |
0x0012: 0x001D | Reserved | — |
0x001F | MAC Reset Control Register | — |
0x0020: 0x003F | TX Configuration and Status Registers | MAC TX |
0x0040: 0x005F | TX Flow Control Registers | MAC TX |
0x0060: 0x006F | Reserved | — |
0x0070 | Reserved | — |
0x0071: 0x009F | Reserved | — |
0x00A0: 0x00FF | RX Configuration and Status Registers | MAC RX |
0x0100: 0x010C | TX Timestamp Registers | MAC TX |
0x0120: 0x012C | RX Timestamp Registers | MAC RX |
0x0140: 0x023F | Statistics Registers | MAC TX, MAC RX |
0x0240: 0x0241 | ECC Registers | MAC TX, MAC RX |