Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 4/01/2024
Public

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Document Table of Contents

3.2. Interfaces

Table 8.   Interfaces
Interfaces Description
Avalon® streaming interface

The client-side interface of the MAC employs the Avalon® streaming protocol, which is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of the data (sink). The key properties of this interface include:

  • Frame transfers marked by startofpacket and endofpacket signals.
  • Signals from source to sink are qualified by the valid signal.
  • Errors marking a current packet are aligned with the end-of-packet cycle.
  • Use of the ready signal by the sink to backpressure the source.

In the MAC IP core, the Avalon® streaming interface acts as a sink in the TX datapath and source in the RX datapath. This interface supports packets, backpressure, and error detection. It operates at either 312.5 MHz or 156.25 MHz depending on the operating mode. The ready latency on this interface is 0.

Avalon® memory-mapped Control and Status Register Interface The Avalon® memory-mapped control and status register interface is an Avalon® memory-mapped slave port. This interface uses word addressing which provides access to the configuration and status registers, and statistics counters.
XGMII

For 10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode, the network-side interface of the MAC IP core implements the XGMII protocol. The XGMII consists of 32-bit data bus and 4-bit control bus operating at 312.5 MHz with TX/RX XGMII valid signal to reflect the data rate accordingly for the multiple Ethernet speed lower than 10G. The data bus carries the MAC frame with the most significant byte occupying the least significant lane.

GMII

In 1G/2.5G operating mode, the network-side interface of the MAC IP core implements 16 bits wide GMII protocol. This 16-bit interface supports 2.5G operations at 156.25 MHz and 1G operations at 62.5 MHz.

For 10M/100M/1G/2.5G variant , the 10M/100M operating mode uses 16 bits wide GMII protocol with TX /RX clock enabled to downsample the data rate /10 and /100. No MII interfaces are available.

Figure 8. Interface SignalsThe inclusion and width of some signals depend on the operating mode and features selected.