Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX Datapath 4.4. RX Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. TX Datapath x
4.3.1. TX MAC 4.3.2. TX PCS 4.3.3. PMA
4.3.1. TX MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. TX Avalon® Streaming Filter
4.4. RX Datapath x
4.4.1. RX MAC 4.4.2. RX PCS
4.4.1. RX MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

7.4. Pause/PFC Flow Control

Table 30.  TX Flow Control Registers
Addr Bit Name Description Reset Access
0x600 31:0 TX Flow Control Revision ID Provide 32-bit TX Flow Control Revision ID. 0x0916_2016 RO
0x601 31:0 TX Flow Control Scratch Pad Provide 32-bit TX Flow Control Scratch Pad Value. 0 RW
0x602 31:0 TX Flow Control IP Core Variant 0 First 4 characters of IP variation identifier ASCII string, "40GE FCTx CSR" 0x35304745 RO
0x603 31:0 TX Flow Control IP Core Variant 1 Next 4 characters of IP variation identifier ASCII string. 0x4643_5478 RO
0x604 31:0 TX Flow Control IP Core Variant 2 Final 4 characters of IP variation identifier ASCII string 0x0043_5352 RO
0x605 7:0

TX Flow Control Enable

Enables the IP to generate XON and XOFF Pause/PFC flow control frames to the remote partner. The following encodings are defined:
  • 0: XON or XOFF Pause/PFC flow control is disabled.
  • 1: XON or XOFF Pause/PFC flow control is enabled.

You can change this field dynamically.

 0xff RW
31:8 Reserved Reserved. 0 RO
0x606 7:0 TX Flow Control CSR XON/XOFF Request 0 XON/XOF flow control frame request bit 0. Interpretation depends on whether the IP is in 1-bit FC request mode or in 2-bit FC request mode. This register affects a flow control queue only if the corresponding bit of the TX Flow Control Enable register has the value of 1.

The following encodings are defined for 1-bit mode.

  • 0 = No request
  • 0 to 1 = Generate XOFF request
  • 1 = Continue to generate XOFF request
  • 1 to 0 = Generate XON request

The following encodings are defined for 2-bit mode.

  • 00 = No request
  • 01 = XON request
  • 10 = XOFF request
  • 11 = Invalid

You can modify the value of this field dynamically.

 0 RW
15:8 Reserved Reserved 0 RO
23:16 TX Flow Control CSR XON/XOFF Request 1

In conjunction with Flow Control XON/XOFF Request 0 specifies a 2-bit request for XON/XOFF flow control frame transmission. This bit is the upper bit of the 2-bit control field.

You can change the value of this field dynamically.

 0 RW
31:24 Reserved Reserved. 0 RO
0x607 31:0 Reserved Reserved. 0 RO
0x608 15:0 Reserved Reserved. 0 RO
31:16 Reserved Reserved. 0 RO
0x609 15:0 Reserved Reserved. 0 RO
31:16 Reserved Reserved. 0 RO
0x60A 0

TX Pause Enable

1-bit

Determines whether receiving a valid Pause frame stops TX user data transmission.

  • 0: Transmission is not stopped
  • 1: Transmission stops

You cannot change the value of this field dynamically.

 0 RW
31:1 Reserved Reserved. 0 RO
0x60B 31:0 Reserved Reserved. 0 RO
0x60C 31:0 Reserved Reserved. 0 RO
0x60D 31:0 TX Flow Control Destination Address Lower

Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field.

You cannot modify the value of this field dynamically.

 0xC2000001 RW
0x60E 15:0 TX Flow Control Destination Address Upper

Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

 0x0180 RW
31:16   Reserved. 0 RO
0x60F 31:0 TX Flow Control Source Address Lower

Specifies the 48-bit Source Address of flow control frame. Contains the 32 LSB of the address field.

0xCBFC5ADD RW
0x610 15:0 TX Flow Control Source Address Upper

Specifies the 48-bit Source Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

 0xE100 RW
31:16 Reserved Reserved. 0 RO
0x620 + (QN), where QN = 0 to 7 15:0

TX Flow Control Quanta

16-bit per FCQN

Specifies the pause quanta of Pause/PFC flow control frames to be sent to remote partner.

You cannot modify the value of this field dynamically.

 0xFFFF RW
31:16 Reserved Reserved. 0 RO
0x628 + (QN), where QN = 0 to 7 15:0

TX Flow Control Signal XOFF Request Hold Quanta

16-bit per FCQN

Specifies the separation between 2 consecutive XOFF flow control frames.

You cannot modify the value of this field dynamically.

 0xFFFF RW
31:16 Reserved Reserved. 0 RO
0x640 0

TX Flow Control Select

1-bit

Specifies whether the TX hardware generates Pause or PFC frames. Affects only PFC Queue 0.

Usage example:

You can synthesize a single PFC queue and use it for both Pause and PFC purpose.

  • 1'b0: Pause
  • 1'b1: PFC

You cannot modify the value of this field dynamically.

 1 RW
31:1 Reserved. Reserved. 0 RO
0x641 FCQN-1:0

TX 2-bit Flow Control Request Mode

1-bit per FCQN

Determines whether the TX Flow Control CSR XON/XOFF Request register or the pause_insert_tx0 and pause_insert_tx1 signals control XON/XOFF mode in 2-bit control mode.

  • 0: The pause_insert_tx0 and pause_insert_tx1 signals control requests
  • 1: The TX Flow Control CSR XON/XOFF Request register fields control requests

You cannot modify the value of this field dynamically.

 0 RW
16

TX Flow Control Request Mode

1 bit for all FCQN

Determines whether the IP is in TX flow control 1-bit mode or 2-bit mode.

  • 0: Use 1-bit mode to make TX flow control requests
  • 1: Use 2-bit mode to make TX flow control requests
 0 RW
31:17 Reserved Reserved. 0 RO
Table 31.  RX Flow Control Registers
Addr Bit Name Description Reset Access
0x700 31:0 RX Flow Control Revision ID Provide 32-bit RX Flow Control Revision ID. 0x09162016 RO
0x701 31:0 RX Flow Control Scratch Pad Provide 32-bit RX Flow Control Scratch Pad Value. 0 RW
0x702 31:0 RX Flow Control IP Core Variant 0

First 4 characters of IP variation identifier ASCII string, "40GE FCTx CSR".

 0x35304745 RO
0x703 31:0 RX Flow Control IP Core Variant 1 Next 4 characters of IP variation identifier ASCII string. 0x4643_5278 RO
0x704 31:0 RX Flow Control IP Core Variant 2 Final 4 characters of IP variation identifier ASCII string. 0x0043_5352 RO
0x705 7:0

RX PFC Enable

Determines whether receiving a valid PFC frame causes the PFC duration user interface to indicate a valid pause quanta duration to the user logic.

0: Disable

1: Enable

You cannot modify the value of this field dynamically.

   RW
31:8 Reserved Reserved. 0 RO
0x706 0 Reserved Reserved. 0 RO
7:1 Reserved Reserved. 0 RO
8 Reserved Reserved. 0 RO
31:9 Reserved Reserved. 0 RO
0x707 31:0 RX Flow Control Destination Address Lower

Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field.

You cannot modify the value of this field dynamically.

Incoming pause frame DA need to match with this address to have flow control working.

 0xC2000001 RW
0x708 15:0 RX Flow Control Destination Address Upper

Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

Incoming pause frame DA need to match with this address to have flow control working.

 0x0180 RW
31:16 Reserved Reserved, 0 RO
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