Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX Datapath 4.4. RX Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. TX Datapath x
4.3.1. TX MAC 4.3.2. TX PCS 4.3.3. PMA
4.3.1. TX MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. TX Avalon® Streaming Filter
4.4. RX Datapath x
4.4.1. RX MAC 4.4.2. RX PCS
4.4.1. RX MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs

Table 33.  Comparison Between Low Latency 40G Ethernet Intel® FPGA IP (alt_e40), Low Latency E-Tile 40G Ethernet Intel® FPGA IP (alt_e40c3), and Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40)

Property

Low Latency 40G Ethernet Intel® FPGA IP

(alt_e40)

Low Latency E-Tile 40G Ethernet Intel® FPGA IP

(alt_e40c3)

Low Latency 40G Ethernet Intel® FPGA IP

(intel_eth_e40)
Transceiver tile support L-Tile, H-Tile E-Tile GTS Transceiver
Device family support

Stratix® 10

Stratix® 10 and Agilex™ 7

Agilex™ 5

Reset

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.
Client interface width

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 128-bit data bus

Avalon® streaming transmitter interface readyLatency Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter).
Preamble passthrough Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When enabled, In RX preamble pass-through mode, the IP passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet and In TX preamble pass through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Interface to transceiver TX PLL You must instantiate a single TX PLL IP to connect to the single tx_serial_clk input pin of the Low Latency 40G Ethernet Intel® FPGA IP. Not required. Not required.
Statistics counters Available as a configuration option (parameter). Available as a configuration option (parameter). Available as a configuration option (parameter).
Statistics counter increment vectors l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled.
40GBASE-KR4 Available as a configuration option. Configurable support for 40GBASE-KR4 or 40GBASE-CR4. Implements the IEEE Backplane Ethernet Standard 802.3-2012. Not supported. Not supported.
Flow control Available as a configuration option (parameter). Available as a configuration option (parameter). Available as a configuration option (parameter).
1588 PTP support Not supported. Not supported. Not supported.
Enable alignment of EOP on FCS word Always turned on. Always turned on. Always turned on.
Minimum average interpacket gap (IPG) Value is 12 bytes. Value is 12 bytes. Value is 12 bytes.
PHY Reference Frequency (MHz)

644.53125

322.265625

 156.25 156.25
Synchronous Ethernet (SyncE) Supported Supported Supported
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