Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX Datapath 4.4. RX Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. TX Datapath x
4.3.1. TX MAC 4.3.2. TX PCS 4.3.3. PMA
4.3.1. TX MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. TX Avalon® Streaming Filter
4.4. RX Datapath x
4.4.1. RX MAC 4.4.2. RX PCS
4.4.1. RX MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

4.6. Link Fault Signaling Interface

Link fault signaling reflects the health of the link. It operates between the remote Ethernet device Reconciliation Sublayer (RS) and the local Ethernet device RS. The link fault modules communicate status during the interframe period. Flow control alleviates congestion at either the local or remote link partner.

Local Fault (LF)

If an Ethernet PHY sublayer detects a fault that makes the link unreliable, it notifies the RS of the local fault condition. If unidirectional is not enabled, the core follows Clause 46. The RS stops sending MAC data, and continuously generates a remote fault status on the TX datapath. After a local fault is detected, the RX PCS modifies the MII data and control to send local fault sequence ordered sets. Refer to the Link Fault Signaling Based On Configuration and Status table.

The RX PCS cannot recognize the link fault under the following conditions:

  • The RX PCS is not fully aligned.
  • The bit error rate (BER) is high.

Remote Fault (RF)

If unidirectional is not enabled, the core follows Clause 46. If the RS receives a remote fault status, the TX datapath stops sending MAC data and continuously generates idle control characters. If the RS stops receiving fault status messages, it returns to normal operation, sending MAC client data. Refer to the Link Fault Signaling Based On Configuration and Status table below.

Link Status Signals

The MAC RX generates two link fault signals: local_fault_status and remote_fault_status.
Note: These signals are real time status signals that reflect the status of the link regardless of the settings in the link fault configuration register.
This register is generated only if you turn on Enable link fault generation . The MAC TX interface uses the link fault status signals for additional link fault signaling.
Table 12.  Link Fault Signaling Based On Configuration and StatusFor more information about the LINK_FAULT register, refer to TX MAC Registers.
LINK_FAULT Register (0x405) Real Time Link Status Configured TX Behavior Comment
Bit [0] Bit [3] Bit [1] Bit [2]

LF Received

RF Received

TX Data

TX RF

1'b0 Don't care Don't care Don't care Don’t care Don’t care On Off

Disable Link fault signaling on TX.

RX still reports link status.

TX side Link fault signaling disabled on the link.

TX data and idle.
1'b1 1'b1 Don't care Don't care Don't care Don't care Off On

Force RF.

TX: Stop data. Transmit RF only
1'b1 1'b0 1'b1 1'b1 Don't care Don't care On Off

Unidir: Backwards compatible.

TX: Transmit data and idle. No RF.
1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 On On

Unidir: LF received.

TX: Transmit data 1 column IDLE after end of packet and RF

1'b1 1'b0 1'b1 1'b0 1'b0 1'b1 On Off

Unidir: RF receives

TX: Transmit data and idle. No RF.
1'b1 1'b0 1'b1 1'b0 1'b0 1'b0 On Off

Unidir: No link fault

TX: Transmit data and idle. No RF.
1'b1 1'b0 1'b0 Don't care 1'b1 1'b0 Off On

Bidir: LF received

TX: Stop data. Transmit RF only.
1'b1 1'b0 1'b0 Don't care 1'b0 1'b1 Off Off

Bidir: RF received

TX: Stop data. Idle only. No RF.
1'b1 1'b0 1'b0 Don’t care 1'b0 1'b0 On Off

Bidir: No link fault

TX: Transmit data and idle. No RF.
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