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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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4.3.7. PMA
The PMA layer uses four transceiver channels to get the four required physical lanes. Each physical lane operates at 10.3125 Gbps. The interface width is 66 bits wide per lane giving a total PMA data width of 264 bits. The reset controller resides inside the GTS PHY transceiver. The serial clocks are generated inside the PHY.
In the Low Latency 40G Ethernet design for Agilex™ 5 devices, the PMA interface uses 80 bits per PCS lane.