Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX Datapath 4.4. RX Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. TX Datapath x
4.3.1. TX MAC 4.3.2. TX PCS 4.3.3. PMA
4.3.1. TX MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. TX Avalon® Streaming Filter
4.4. RX Datapath x
4.4.1. RX MAC 4.4.2. RX PCS
4.4.1. RX MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

7.1. PHY Registers

Table 27.  PHY Registers
Addr Name Description Reset Access
0x00 REVID IP PHY module revision ID. 0x0627 2016 RO
0x01 SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x02 PHY_NAME_0 First characters of IP variation identifier string. 0x0000 3430 RO
0x03 PHY_NAME_1 Next characters of IP variation identifier string. 0x0000 4745 RO
0x04 PHY_NAME_2 Final characters of IP variation identifier string. 0x0070 6373 RO
0x10 PHY_CONFIG PHY configuration registers. The following bit fields are defined:
  • Bit[0]: eio_sys_rst. Full system reset (except registers).
  • Bit[1]: soft_txp_rst. TX soft reset.
  • Bit[2]: soft_rxp_rst. RX soft reset.
  • Bit[3]: Reserved.
  • Bit[4]: set_ref_lock
  • Bits[31:5]: Reserved.
 0bxxxx xxxx xxxx xxxx xxxx xxxx xx00 x000 RW
0x12 WORD_LOCK When asserted, indicates that the virtual channel has identified 66-bit block boundaries in the serial data stream. 0xXXXX XXX0 RO
0x14 EIO_FLAG_SEL Supports indirect addressing of individual FIFO flags in the PCS Direct PHY IP. This is a binary encoded value and the flags are set as below for bits [20:0]:
  • 3'b000: TX FIFO full
  • 3'b001: TX FIFO empty
  • 3b010: TX FIFO partially full
  • 3'b011: TX FIFO partially empty
  • 3b100: RX FIFO full
  • 3b101: RX FIFO empty
  • 3b110: RX FIFO partially full
  • 3b111: RX FIFO partially empty
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 RW
0x15 EIO_FLAGS PCS indirect data. To read a FIFO flag, set the corresponding bit in the PHY_PCS_INDIRECT_ADDR register. After you specify the flag in the PHY_PCS_INDIRECT_ADDR register, each bit [n] in the PHY_PCS_INDIRECT_ADDR register has the value of the corresponding transceiver FIFO flag. 0xXXXX XXX0 RO
0x21 EIO_FREQ_LOCK Each asserted bit indicates that the corresponding lane RX clock data recovery (CDR) phase-locked loop (PLL) is locked. 0xXXXX XXX0 RO
0x22 PHY_CLK The following encodings are defined:
  • Bit[0]: Indicates if the TX PCS is ready
  • Bit [1]: Indicates if the TX MAC PLL is locked.
  • Bit[2]: Indicates if the RX PLL is locked.
 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 RO
0x23 FRM_ERR

Each asserted bit indicates that the corresponding virtual lane has a frame error. These bits are sticky. You clear them with the PHY_SCLR_FRAME_ERROR register.

If the IP loses word lock, it clears this register.

 0xXXXX XXX0 RO
0x24 SCLR_FRM_ERR Synchronous clear for PHY_FRAME_ERROR register. Write a value of 1 to this register to clear the PHY_FRAME_ERROR register. Then need to write 0 to this register to let PCS RX working properly. Keep this register as 1 causes PCS link lost. 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 RW
0x25 EIO_RX_SOFT_PURGE_S Set bit [0] to clear the RX FIFO for all four physical lanes.
  • Bit[11]: If set to 1, disables the bitslip request from PCS to PMA.
  • Bit[12]: If set to 1, disables the reset request from PCS to PMA. To use the transceiver toolkit, this bit must be set to 1.
0bx0 0xxx xxxx xxx0 RO
0x26 RX_PCS_FULLY_ALIGNED_S Indicates the RX PCS is fully aligned and ready to accept traffic.
  • Bit[0]: RX PCS fully aligned status.
 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 RO
0x28 AM_LOCK When asserted, indicates that the physical channel has identified virtual lane alignment markers in the data stream. This is a one-bit signal. 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0  
0x29 LANE_DESKEWED
The following encodings are defined:
  • Bit [0]: Indicates all lanes are deskewed.
  • Bit [1]: When asserted indicates a change in lanes deskewed status. To clear this sticky bit, write 1'b1 to the corresponding bit of the SCLR_FRM_ERR register.

After reset, the lane_deskewed value is undefined before RX clock is up

 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx RO
0x30 PCS_VLANE The following encodings are defined:
  • Bit[1:0]: Virtual index for physical lane 0.
  • Bit[3:2]: Virtual index for physical lane 1.
  • Bit[5:4]: Virtual index for physical lane 2.
  • Bit[7:6]: Virtual index for physical lane 3.
 0xXXXX XX00 RO
0x31 PHY_RX_DELAY Test and debug feature to test deskew. Allows you to insert a programmable skew on one physical channel. It is a 6 bit register with these fields:
  • Bit[0]: Allows you to you to shift 33 bits for incoming stream in physical channel 0, effectively inserting sew on two of the virtual lanes.
  • Bit[5:1]: Allows you to insert a 1-32 word delay on the two virtual channels arriving on physical lane 0. To use bits[5;1], you must set an RX PCS dynamic parameter that is not exposed at the top level (DYNAMIC_SKEW).
Note: Due to the FIFO based implementation of word-delay logic, the minimum value for word-delay (Bits 1-5) is 2 corresponding to a delay of one cycle. This ensures that the FIFOs read/write pointers are collision free.
0bxxxx xxxx xxxx xxxx xxxx xxxx xx00 0000 RW
0x41 KHZ_RX The register indicates the value of RX clock (clk_rxmac) frequency. Apply the following definition for the frequency value:

[(Register value 2 * clk_status)/10] KHz

0x0000 0000 RO
0x42 KHZ_TX The register indicates the value of TX clock (clk_txmac) frequency. Apply the following definition for the frequency value:

[(Register value 2 * clk_status)/10] KHz

0x0000 0000 RO
1 X means "Don't Care".
2 Register value convert in decimal.
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