Cyclone® V GT FPGA Development Kit User Guide

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ID 792833
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Kit Features 2. Getting Started 3. Software Installation 4. Development Board Setup 5. Board Update Portal 6. Board Test System 7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide A. Programming the Flash Memory Device B. Additional Information
1. Kit Features x
1.1. Hardware 1.2. Software
1.2. Software x
1.2.1. Intel® Quartus® Prime Software 1.2.2. Cyclone® V GT FPGA Development Kit Installer
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. References for Getting Started
3. Software Installation x
3.1. Installing the Intel® Quartus® Prime Subscription Edition Software 3.2. Activating Your License 3.3. Installing the Development Kit 3.4. Installing the Intel® FPGA Download Cable II Driver
4. Development Board Setup x
4.1. Setting Up the Board 4.2. Factory Default Switch and Jumper Settings 4.3. Configuring the MAX® V Device to Program EPCQ 4.4. Restoring the MAX® V CPLD to the Factory Settings 4.5. Restoring the Flash Device to the Factory Settings 4.6. Configuring the FPGA Using the Intel® Quartus® Prime Programmer
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page 5.2. Using the Board Update Portal to Write User Designs
6. Board Test System x
6.1. Preparing to Run the Board Test System 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. The Power Monitor 6.5. The Clock Control
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The DDR3x40 and DDR3x64 Tabs 6.3.6. The HSMA Tab 6.3.7. The HSMB Tab
6.3.2. The System Info Tab x
6.3.2.1. Power Tree 6.3.2.2. Power Monitor 6.3.2.3. Board Information 6.3.2.4. MAX® V Registers 6.3.2.5. JTAG Chain
6.3.3. The GPIO Tab x
6.3.3.1. Character LCD and Display 6.3.3.2. User DIP Switches 6.3.3.3. User LEDs 6.3.3.4. Push Buttons
6.3.4. The Flash Tab x
6.3.4.1. Read and Start Address 6.3.4.2. Range 6.3.4.3. Write 6.3.4.4. CFI Query 6.3.4.5. Reset 6.3.4.6. Erase 6.3.4.7. Flash Memory Table and Flash Memory Map
6.3.5. The DDR3x40 and DDR3x64 Tabs x
6.3.5.1. Start 6.3.5.2. Stop 6.3.5.3. Performance Indicators 6.3.5.4. Error Control 6.3.5.5. Number of Addresses to Write and Read
6.3.6. The HSMA Tab x
6.3.6.1. Start, Stop 6.3.6.2. XCRV, LVDS, CMOS
6.3.7. The HSMB Tab x
6.3.7.1. Start, Stop 6.3.7.2. XCRV and CMOS
6.4. The Power Monitor x
6.4.1. Power Monitor Features 6.4.2. Power Monitor Controls
6.4.2. Power Monitor Controls x
6.4.2.1. General Information 6.4.2.2. Power Information 6.4.2.3. Power Graph 6.4.2.4. Graph Settings 6.4.2.5. Reset
6.5. The Clock Control x
6.5.1. Clock Control Features 6.5.2. Clock Control Controls
6.5.2. Clock Control Controls x
6.5.2.1. Serial Port Registers 6.5.2.2. fXTAL 6.5.2.3. Target Frequency 6.5.2.4. Clear 6.5.2.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Converting Additional Files A.5. Programming Flash Memory Using the Nios® II EDS A.6. Programming Flash Memory Using the Board Update Portal
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Kit Features
2. Getting Started
3. Software Installation
4. Development Board Setup
5. Board Update Portal
6. Board Test System
7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide
A. Programming the Flash Memory Device
B. Additional Information

A.5. Programming Flash Memory Using the Nios® II EDS

The Nios® II EDS offers a nios2-flash-programmer utility to program the flash memory directly. To program the .flash files or any compatible .srec file to the board using nios2-flash-programmer, do the following:

  1. Set the SW4.3 DIP switch to the FACT ON (logic 0) to load the Board Update Portal design from flash memory on power up.
  2. Attach the Intel® FPGA Download Cable and power up the board.
  3. If the board has powered up and the LCD displays either Connecting...or a valid IP address (such as 152.198.231.75), proceed to step 8. If no output appears on the LCD or if the Config Done LED (D7) does not illuminate, continue to step 4 to load the FPGA with a flash-writing design.
  4. Run the Intel® Quartus® Prime Programmer to configure the FPGA with a .sof capable of flash programming. Refer to Restoring the MAX® V CPLD to the Factory Settings for more information.
  5. Click Add File and select <install dir>\kits\cycloneVGT_5cgtfd9ef35_fpga\factory_recovery\c5gt_fpga_bup.sof.
  6. Turn on the Program/Configure option for the added file.
  7. Click Start to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100%. The Config Done LED (D7) illuminates indicating that the flash device is ready for programming.
  8. In the Nios® II command shell, navigate to the <install dir>\kits\cycloneVGT_5cgtfd9ef35_fpga\factory_recovery directory.

    You can also navigate to the directory of the .flash files you created in Creating Flash Files Using the Nios® II EDS.

  9. Type the following Nios® II EDS command:
    nios2-flash-programmer --base=0x00000000 <yourfile>_hw.flash
  10. After programming completes, if you have a software file to program, type the following Nios® II EDS command:
    nios2-flash-programmer --base=0x00000000 <yourfile>_sw.flash
  11. Set the SW4.3 DIP switch to the FACT OFF (logic 1) position and power cycle the board.

Programming the board is now complete.

To restore flash memory, refer to Restoring the Flash Device to the Factory Settings.

For more information about the nios2-flash-programmer utility, refer to the Nios® II Flash Programmer User Guide.

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