Cyclone® V GT FPGA Development Kit User Guide

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ID 792833
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Kit Features 2. Getting Started 3. Software Installation 4. Development Board Setup 5. Board Update Portal 6. Board Test System 7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide A. Programming the Flash Memory Device B. Additional Information
1. Kit Features x
1.1. Hardware 1.2. Software
1.2. Software x
1.2.1. Intel® Quartus® Prime Software 1.2.2. Cyclone® V GT FPGA Development Kit Installer
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. References for Getting Started
3. Software Installation x
3.1. Installing the Intel® Quartus® Prime Subscription Edition Software 3.2. Activating Your License 3.3. Installing the Development Kit 3.4. Installing the Intel® FPGA Download Cable II Driver
4. Development Board Setup x
4.1. Setting Up the Board 4.2. Factory Default Switch and Jumper Settings 4.3. Configuring the MAX® V Device to Program EPCQ 4.4. Restoring the MAX® V CPLD to the Factory Settings 4.5. Restoring the Flash Device to the Factory Settings 4.6. Configuring the FPGA Using the Intel® Quartus® Prime Programmer
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page 5.2. Using the Board Update Portal to Write User Designs
6. Board Test System x
6.1. Preparing to Run the Board Test System 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. The Power Monitor 6.5. The Clock Control
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The DDR3x40 and DDR3x64 Tabs 6.3.6. The HSMA Tab 6.3.7. The HSMB Tab
6.3.2. The System Info Tab x
6.3.2.1. Power Tree 6.3.2.2. Power Monitor 6.3.2.3. Board Information 6.3.2.4. MAX® V Registers 6.3.2.5. JTAG Chain
6.3.3. The GPIO Tab x
6.3.3.1. Character LCD and Display 6.3.3.2. User DIP Switches 6.3.3.3. User LEDs 6.3.3.4. Push Buttons
6.3.4. The Flash Tab x
6.3.4.1. Read and Start Address 6.3.4.2. Range 6.3.4.3. Write 6.3.4.4. CFI Query 6.3.4.5. Reset 6.3.4.6. Erase 6.3.4.7. Flash Memory Table and Flash Memory Map
6.3.5. The DDR3x40 and DDR3x64 Tabs x
6.3.5.1. Start 6.3.5.2. Stop 6.3.5.3. Performance Indicators 6.3.5.4. Error Control 6.3.5.5. Number of Addresses to Write and Read
6.3.6. The HSMA Tab x
6.3.6.1. Start, Stop 6.3.6.2. XCRV, LVDS, CMOS
6.3.7. The HSMB Tab x
6.3.7.1. Start, Stop 6.3.7.2. XCRV and CMOS
6.4. The Power Monitor x
6.4.1. Power Monitor Features 6.4.2. Power Monitor Controls
6.4.2. Power Monitor Controls x
6.4.2.1. General Information 6.4.2.2. Power Information 6.4.2.3. Power Graph 6.4.2.4. Graph Settings 6.4.2.5. Reset
6.5. The Clock Control x
6.5.1. Clock Control Features 6.5.2. Clock Control Controls
6.5.2. Clock Control Controls x
6.5.2.1. Serial Port Registers 6.5.2.2. fXTAL 6.5.2.3. Target Frequency 6.5.2.4. Clear 6.5.2.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Converting Additional Files A.5. Programming Flash Memory Using the Nios® II EDS A.6. Programming Flash Memory Using the Board Update Portal
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Kit Features
2. Getting Started
3. Software Installation
4. Development Board Setup
5. Board Update Portal
6. Board Test System
7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide
A. Programming the Flash Memory Device
B. Additional Information

5.1. Connecting to the Board Update Portal Web Page

To connect to the Board Update Portal web page, ensure that you have the following items setup and installed:

  • A PC with a connection to a working Ethernet port on a DHCP enabled network.
  • A separate working Ethernet port connected to the same network for the board.
  • The Ethernet and power cables that are included in the kit.

To connect to the Board Update Portal web page, perform the following:

  1. With the board powered down, set the SW4.3 DIP switch to the FACT ON (logic 0) position.
  2. Attach the Ethernet cable from the board to your LAN.
  3. Power up the board. The board connects to the LAN’s gateway router and obtains an IP address. The LCD on the board displays the IP address.
  4. Start a web browser on a PC that is connected to the same network, and enter the IP address from the LCD into the browser address bar. The Board Update Portal web page appears in the browser.

You can click Cyclone® V GT FPGA Development Kit on the Board Update Portal web page to access the kit’s home page for documentation updates and additional new designs.

You can also navigate directly to the Cyclone® V GT FPGA Development Kit page of the Intel website to determine if you have the latest kit software.

Related Information
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