Visible to Intel only — GUID: zwg1683045146820
Ixiasoft
Visible to Intel only — GUID: zwg1683045146820
Ixiasoft
2.1.3.4. Reset Flow
The Agilex™ 5 E-Series Virtual Platform supports all key reset flows described in the Agilex™ 5 E-Series HPS Technical Reference Manual. Reset flows initiated by the CPU are simulated through the same mechanism in which the CPU writes to the appropriate addresses (that is, reset manager device).
Resets triggered by external hardware signaling are simulated using Intel® Simics® commands.
The following table describes the supported reset types and how to exercise them from a simulation:
Reset Type | Exercise Method | Description |
---|---|---|
Power-on Reset |
Not Supported. |
The power-on reset is not supported because its effect is equivalent to restarting the simulation in a virtual platform simulation. However, if this is required for some exceptional use cases, you can trigger the cold reset instead, as this resets most of the domains. |
HPS Cold Reset |
system.board.hps-cold-reset | Simulates toggling the pin using the command registered in the board component. |
HPS Warm Reset |
system.board.fpga.soc_inst.hps_subsys.agilex_hps.hps-warm-reset | Simulates a warm reset of the HPS without needing to trigger any other event. This type of reset is not enabled through external means in hardware. The command is registered in the HPS component. |
Watchdog reset |
Software based |
The watchdog timer peripheral in the HPS can be configured and enabled through software. When the watchdog expires, the HPS is reset. A warm reset is supported after the watchdog timer expires. |
Target Script Simulating a Warm and Cold Reset
The following example captures a target script issuing warm and cold reset in a simulation where the U-Boot SPL to U-Boot SSBL boot flow is being exercised. The example uses a script branch to set few breakpoints on messages displayed in the serial console. Initially, it waits for a message that U-Boot SSBL prints and then, the script issues a warm reset. At this time, the HPS is reset, and U-Boot SPL restarts printing the detected type of reset, which at this time is a warm reset. After the warm reset, the script waits again for U-Boot SSBL to print the same message and issues a cold reset. The U-Boot SPL is executed again, indicating that the reset type is a cold reset.
$sd_image_filename = "sdcard.img" $fsbl_image_filename = "u-boot-spl-dtb.bin" $hps_cpu_freq_mhz = 800 $create_hps_sd_card = TRUE run-command-file "targets/agilex5e-universal/agilex5e-universal.simics" script-branch{ # Wait for U-Boot SSBL bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "CPU: Intel FPGA SoCFPGA Platform" echo "Breakpoint hit..." # Generate a Warm Reset system.board.fpga.soc_inst.hps_subsys.agilex_hps.hps-warm-reset bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "Reset state: Warm [from SDM]" echo "Warm reset detected by U-Boot SPL" # Wait for U-Boot SSBL bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "CPU: Intel FPGA SoCFPGA Platform" echo "Breakpoint hit..." # Generate a Cold Reset system.board.hps-cold-reset bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "Reset state: " echo "Cold reset detected by U-Boot SPL" }
The following output is observed in the Intel® Simics® CLI after executing the above target script:
Connections: hps2fpga_0_down : system.board.fpga.soc_inst.example_design:design_mem_conn hps_conn : system.board.fpga.soc_inst.hps_subsys.emif:emif_conn : Breakpoint hit... Warm reset detected by U-Boot SPL Breakpoint hit... Cold reset detected by U-Boot SPL