Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 Virtual Platform User Guide

Download PDF
ID 786901
Date 11/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 Intel® Simics® Virtual Platforms 3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History for Intel Simics Simulator for Intel FPGAs Agilex 5 Virtual Platform User Guide
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 Universal Virtual Platform
2.1. Agilex™ 5 Universal Virtual Platform x
2.1.1. Agilex™ 5 Universal Virtual Platform Overview 2.1.2. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 Universal Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 Universal Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design led_pio Component From Intel® Simics® CLI Exercise Interrupt Triggering in Peripheral Subsystem from Intel® Simics® CLI 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. Agilex™ 5 HPS Component and Stepping Silicon Features Selection
3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 HPS Components 3.1.6. Agilex™ 5 B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 Intel® Simics® Virtual Platforms
3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Intel FPGAs Agilex 5 Virtual Platform User Guide

2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design

led_pio Component From Intel® Simics® CLI Exercise

The Intel® Simics® model of the led_pio component allows to emulate having connected a set of up to 32 LEDs in the virtual platform. This component uses its DATA register to control the state of each one of the LEDs (one bit per LED) and also to read back the current state.

The following table shows some of the methods which you can set and read the state of the LEDs from an Intel® Simics® CLI command. The first and second rows show how this can be done by directly accessing the DATA register with the write-device-reg and read-device-register commands. The third and fourth row shows how the DATA register is accessed through the physical offset in which the DATA register is located (at 0x10080 offset under the lwhps2fpga bridge mapping offset):

Table 12.  CLI Commands to Read the LED State
Task Command
Write through register write-device-reg system.board.fpga.soc_inst.periph_subsys.led_pio.bank.regs.DATA <led_state>
Read through register read-device-reg system.board.fpga.soc_inst.periph_subsys.led_pio.bank.regs.DATA
Write by offset set 0x20010080 <led_state> 4
Read by offset get 0x20010080 4

Interrupt Triggering in Peripheral Subsystem from Intel® Simics® CLI

The button_pio and dipsw_pio components in the peripheral subsystem are provided with the capability to trigger interrupts to the HPS. These components use the INTERRUPTMASK register to enable the interrupt triggering and to clear the interrupt. Since these components handle GPIO inputs, you can control the signals' state through the port.input_io[].iface.signal interface from the Intel® Simics® CLI. One single input is supported in each component, and the interrupt is triggered on the rising edge of the signal.

The following table shows the commands used to handle the interrupts triggering:

Table 13.  Commands to Handle Interrupts
Task Command
Enabling interrupt write-device-reg system.board.fpga.soc_inst.periph_subsys.button_pio.bank.regs.INTERRUPTMASK 1
write-device-reg system.board.fpga.soc_inst.periph_subsys.dipsw_pio.bank.regs.INTERRUPTMASK 1
   
Triggering interrupt by asserting input signal and observing the state of the signal @conf.system.board.fpga.soc_inst.periph_subsys.button_pio.port.input_io[0].iface.signal.signal_raise()
@conf.system.board.fpga.soc_inst.periph_subsys.dipsw_pio.port.input_io[0].iface.signal.signal_raise()
   
Observing the state of the input signal read-device-reg system.board.fpga.soc_inst.periph_subsys.button_pio.bank.regs.DATA
read-device-reg system.board.fpga.soc_inst.periph_subsys.dipsw_pio.bank.regs.DATA
   
Clearing and disabling the interrupt write-device-reg system.board.fpga.soc_inst.periph_subsys.button_pio.bank.regs.INTERRUPTMASK 0
write-device-reg system.board.fpga.soc_inst.periph_subsys.dipsw_pio.bank.regs.INTERRUPTMASK 0
Note:

To observe the Intel® Simics® CLI message indicating the interrupt triggering, increase the log level in the HPS GIC device using: 

log-level object = system.board.fpga.soc_inst.hps_subsys.agilex_hps.gic level = 4
Level Two Title