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1. About This Document
2. Agilex™ 5 Intel® Simics® Virtual Platforms
3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Intel FPGAs Agilex 5 Virtual Platform User Guide
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. Agilex™ 5 HPS Component and Stepping Silicon Features Selection
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3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models
This chapter describes the Intel® Simics® models of various components integrated into a virtual platform, including the top-level components in a virtual platform, such as the HPS, FPGA, and Board components.
For these device Intel® Simics® models, information such as the Intel® Simics® model availability (the model supported or not supported) and any relevant limitations are provided. Review the limitations to determine if you can or cannot exercise any part of your HPS embedded software in a simulation.
For some components, a list of supported features is provided along with possible configuration parameters. For board components, you can configure the parameters according to your virtual platform requirements.
Each of the device models that are integrated into the Agilex™ 5 HPS model is modeled as closely as possible to the functionality provided by the real hardware, but there might be some limitations that cause the simulation and hardware functionality of a component to differ.
General Component Limitations
The following limitations apply to all components:
- Analog functionality in the IPs is not modeled.
- The IP transactions are not being modeled accurately in terms of timing. Hence, the device modeling operates at the transaction level and the overall functionality of the model is not affected by this limitation. Although most models include a clock in their modeling, the CPU model is the only one that uses this clock to coordinate the instruction fetching and execution. In most models, operations are executed at zero time after receiving any request transaction. This means that when a transaction leaves the CPU (synchronized with the CPU clock), the transaction receiver module processes this and generates a response (if needed) in the same clock cycle.
- Hardware components may include internal RAM to handle data, which normally include some type of data error detection and correction mechanism (ECC). Typically, this protection mechanism is not implemented in the Intel® Simics® models.
- In real hardware, accessing the DDR memory requires that CCU and MPFE components are initialized. This is not true for the Agilex™ 5 Simics model since DDR memory can be accessed without this requirement.