Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 Virtual Platform User Guide

Download PDF
ID 786901
Date 11/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 Intel® Simics® Virtual Platforms 3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History for Intel Simics Simulator for Intel FPGAs Agilex 5 Virtual Platform User Guide
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 Universal Virtual Platform
2.1. Agilex™ 5 Universal Virtual Platform x
2.1.1. Agilex™ 5 Universal Virtual Platform Overview 2.1.2. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 Universal Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 Universal Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. Agilex™ 5 HPS Component and Stepping Silicon Features Selection
3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 HPS Components 3.1.6. Agilex™ 5 B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 Intel® Simics® Virtual Platforms
3. Agilex™ 5 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Intel FPGAs Agilex 5 Virtual Platform User Guide

3.2.2. Security Device Manager (SDM)

The following table indicates the support status of the components integrated into the Secure Device Manager. The table also indicates any component limitations the object created in the Intel® Simics® model of the FPGA component:

Table 19.  Support Status of the Components Integrated into the Secure Device Manager and Their Limitations
Component Supported? Support Status | Limitations | Objects
SDM Mailbox Yes
  • Limitations:
    • SDM mailbox is implemented as a closed box with mailbox functionality (not a fully functional model) supporting a set of commands for generating a response.
    • Registers for HPS to SDM Mailbox interaction are stubbed.
  • Object: system.board.fpga.soc_inst.hps_subsys.sdm.sdm_mailbox
QSPI Controller Yes
  • Limitations:
    • Legacy mode is unimplemented.
    • Write-protect is not supported.
    • QSPI boot is observed slow for JFFS2 file format (use UBIFs for fast boot).
    • DMA transfers are not supported.
    • Execute in Place (XIP) is not implemented.
  • Object: system.board.fpga.soc_inst.hps_subsys.sdm.qspi
Level Two Title