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1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
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2.1.3.5. General Purpose I/O (GPIO) Loopback
The virtual platform supports a model that creates a loopback connection in certain pins in GPIO0 and GPIO1 ports. This feature is implemented at board component level.
The loopback implementation consists of directly connecting GPIO in and out pins of the GPIO ports in both directions to reflect the same state on those pins.
In each GPIO port, the following pairs of pins are connected as shown in the image below:
- [0,1]
- [5,6]
- [18,19]
- [20,21]
Figure 8. General Purpose I/O (GPIO) Loopback