Visible to Intel only — GUID: aub1683045150038
Ixiasoft
Visible to Intel only — GUID: aub1683045150038
Ixiasoft
3.3.1. FPGA Fabric
Three components integrate the FPGA fabric model:
- Peripheral subsystem
- On-Chip memory example design
- FPGA-To-HPS Bridge memory spaces
The following sections provide additional details about these components:
Peripheral Subsystem
The peripheral subsystem is integrated by the components: button_pio, dipsw_pio, and led_pio. Each one of these components corresponds to the Intel® Simics® model of a parallel input/output core that provides a memory-mapped interface to access general-purpose input/output ports through registers read/write operations. In this case, these cores allow to read the state of a signal connected to a push button or a dip switch and also control the state of an LED. These components are mapped under the lwhps2fpga bridge so the HPS software can get/set the current state of the input/output pin through memory access to the specific location in which these components are mapped.
The mapping of the peripheral subsystem under the lwhps2fpga bridge is shown next:
FPGA Fabric Component | Bridge | Size | Start Address | End Address |
---|---|---|---|---|
peripheral subsystem | lwhps2fpga | 512 MB | 0x0020000000 | 0x003FFFFFFF |
The following lines provide more information about the functionality of each one of these components:
- button_pio : Allows to read the state of a pin connected to a push button. One single pin is supported, and the state of the pin can be read through the DATA register, which is a read-only register. This component supports generating an interrupt that can be connected to the HPS. The interrupt is enabled using the INTERRUPTMASK register by assigning a value of ‘1’. The interrupt is triggered on the rising edge of the input signal.
- dipsw_pio : Allows to read the state of a pin connected to a dip switch. One single pin is supported, and the state of the pin can be read through the DATA register, which is a read-only register. This component supports generating an interrupt that can be connected to the HPS. The interrupt is enabled using the INTERRUPTMASK register by assigning a value of ‘1’. The interrupt is triggered on the rising edge of the input signal.
- led_pio : Allows to set the state of a pin connected to an LED. It also allows reading back the state of the pin. Up to 32 pins are supported, and the state of the pins can be set or read through the DATA register (one bit per pin).
The following table shows the internal memory mapping (relative to the address mapping under the lwhps2fpga bridge) of the peripheral components and additional information about the internal registers:
Component | Mapping Address | Range | Register Information | |
---|---|---|---|---|
Offset | Description | |||
button_pio | 0x00010060 | 0x10 | 0x0 | DATA[0:0]- Read state of the button. Read Only. |
0x8 | INTERRUPTMASK[0:0]- Enable('1’)/Disable('0’) the interrupt trigger. When disable, the interrupt is cleared. Read/Write. | |||
dipsw_pio | 0x00010070 | 0x10 | 0x0 | DATA[0:0]- Read state of the button. Read Only. |
0x8 | INTERRUPTMASK[0:0]- Enable('1’)/Disable('0’) the interrupt trigger. When disable, the interrupt is cleared. Read/Write. | |||
led_pio | 0x00010080 | 0x10 | 0x0 | DATA[31:0] – Set and read the state of the LEDs. Read/Write. |
The registers can be accessed directly using the Intel® Simics® CLI through the write-device-reg, read-device-reg commands or using the offset with the write-device-offset and read-device-offset commands. In the case of the button_pio and dipsw_pio components, the above commands cannot be used to emulate pressing the button or changing the state of the switch since these are input devices. In order to perform this, the following commands can be used:
# To set the input simics> @conf.system.board.fpga.soc_inst.periph_subsys.dipsw_pio.port.input_io[0].iface.signal.signal_raise() simics> @conf.system.board.fpga.soc_inst.periph_subsys.button_pio.port.input_io[0].iface.signal.signal_raise() # To clear the input simics> @conf.system.board.fpga.soc_inst.periph_subsys.dipsw_pio.port.input_io[0].iface.signal.signal_lower() simics> @conf.system.board.fpga.soc_inst.periph_subsys.button_pio.port.input_io[0].iface.signal.signal_lower()
On-Chip Memory Example Design
The On-Chip memory IP allows read/write operations from/to the HPS software connected through the hps2fpga bridge.
The mapping of the On-Chip memory example is defined as follows:
Example Design Name |
Bridge |
Size |
Start Address |
End Address |
---|---|---|---|---|
example_design | hps2fpga |
1 MB |
0x0040000000 |
0x00400FFFFF |
The On-Chip memory example design in the FPGA fabric receives a parameter named base_addr that defines an offset value that indicates the mapping of the instance, taking as reference the Start Address value defined in the previous table.
The objects corresponding to the example design are the following:
- system.board.fpga.soc_inst.example_design
FPGA-To-HPS Bridge Memory Spaces
Initiators in the FPGA logic model use these memory spaces to start read/write operations directed to the HPS or SDRAM components.