Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

ID 786901
Date 8/08/2024
Public
Document Table of Contents

3.1.6. Agilex™ 5 E-Series B0 Features Support

The Agilex™ 5 E-Series Simics model offers the flexibility of supporting the A0 or B0 silicon stepping features. The selection of the stepping features is controlled through a parameter in the virtual platform target script in which the device is instantiated. The features described in this document apply to both A0 and B0 steppings, and only the following apply to the B0 stepping:

  • Power management ability to bring up a secondary core by the HPS. This feature implements the PWRCTL_WRT_LOCK register that SDM sets during the boot core bring-up to prevent writing some power manager control registers, but still allow to set the PCHCTLR[TRIGGER_PCH_CPU] bits that allow releasing from reset the secondary cores.
  • Reset controller ability to reset a secondary core from the boot core individually.