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1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
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3.1.5. Additional Agilex™ 5 E-Series HPS Components
The following table lists the support status of components that do not belong to any specific subsystem. The table also shows any component limitations and the object created in the Intel® Simics® model of the Agilex™ 5 E-Series HPS.
Component | Supported? | Limitations | Objects |
---|---|---|
Error Checking and Correction (ECC) Controller | No | N/A |
HPS2FPGA Bridge | Yes | Limitations:
Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.hps2fpga |
Lightweight HPS2FPGA Bridge | Yes | Limitations:
Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.lwhps2fpga |
FPGA2HPS Bridge | Yes | Limitations:
Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.fpga2hps |
FPGA2SDRAM Bridge | Yes | Limitations:
Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.f2sdram |
System Memory Management Unit (SMMU) | Yes |
Limitations:
Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.smmu |