Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping 3.4. Analog Parameter Options
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Asynchronous Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status 7.1.21. HSSI Hotplug Debug Port Control 7.1.22. HSSI Hotplug Debug Port Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

2.2. Supported Features

The IP core handles the frame encapsulation and flow of data between client logic and an Ethernet network through 10Gbps, 25Gbps, 40Gbps, 50Gbps, 100Gbps, 200Gbps and 400Gbps Ethernet PHY with optional Forward Error Correction (FEC). The client data interface is implemented on AXI4-Streaming interface and AXI4-Lite interface for register access.
Table 7.  Supported Ethernet Protocols
Ethernet Channel Tile Support Supported Ports per Subsystem Protocol Lanes FEC PTP AN/LT
10GbE E, F 1-16 10GBASE-KR 1x10.3125 Gbps NRZ lane for Copper Backplane N Y Y1
E, F 1-16 10GBASE-CR 1x10.3125 Gbps NRZ lane for Direct Attach Copper Cable N Y 1 Y1
E, F 1-16 10GBASE-R 1x10.3125 Gbps NRZ lane for Low Loss Connections to External PHY Modules N Y1 Y1
25GbE E, F 1-16 25GBASE-KR 1x25.78125 Gbps NRZ lane for Copper Backplane RSFEC Y1 Y1
E, F 1-16 25GBASE-CR 1x25.78125 Gbps NRZ lane for Direct Attach Copper Cable RSFEC Y1 Y1
E, F 1-16

25GBASE-R AUI

 1x25.78125 Gbps NRZ lane for Low Loss Connections to External PHY Modules RSFEC Y1 Y1
E, F 1-16

25GBASE-R Consortium Link

 1x25.78125 Gbps NRZ lane based on the 25G/50G Consortium Specification RSFEC Y1 Y1
40GbE F only 1-4 40GBASE-KR4 4x10.3125 Gbps NRZ lane for Copper Backplane N N Y
F only 1-4 40GBASE-CR4 4x10.3125Gbps NRZ lane for Direct Attach Copper Cable N N Y
F only 1-4 40GBASE-SR4 4x10.3125Gbps NRZ for optical fiber N N Y
50GbE F only 1-8 50GBASE-KR2 2x25.78125Gbps NRZ for Copper Backplane RSFEC Y Y
F only 1-8 50GBASE-CR2 2x25.78125Gbps NRZ for Direct Attach Copper Cable RSFEC Y Y
F only 1-8 50GAUI-2 2x25.78125Gbps NRZ lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module RSFEC Y Y
F only 1-8 50GAUI-1 1x53.125 Gbps PAM4 KPFEC, ETC Y Y
100GbE E, F 1-4

100GBASE-KR4

 4x25.78125 Gbps Non-Return-to-Zero (NRZ) lanes for Copper Backplane RSFEC Y Y
E, F 1-4

100GBASE-CR4

4x25.78125 Gbps NRZ lanes for Direct Attach Copper Cable RSFEC Y Y
E, F 1-4 CAUI-4

4x25.78125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module

 RSFEC Y Y
E, F 1-4 CAUI-2 2x53.125Gbps PAM4 KPFEC, ETC Y Y
F only 1-4 CAUI-1 1x106.25Gbps PAM4 KPFEC Y Y
200GbE F only 1-2 200GAUI-4 4x53.125 Gbps PAM4 KPFEC, ETC Y Y
F only 1-2 200GAUI-2 2x106.25 Gbps PAM4 KPFEC Y Y
F only 1-2 200GAUI-8 8x25.78125 Gbps PAM4 KPFEC Y Y
400GbE F only 1 400GAUI-8 8x53.125 Gbps PAM4 KPFEC, ETC Y Y
F only 1 400GAUI-4 4x106.24 Gbps Gbps PAM4 KPFEC Y Y
Table 8.  Supported CPRI Protocols
CPRI Channel Tile Support Supported Ports per Subsystem Protocol Lanes RSFEC
2.4G_PMA E 1-16 CPRI 1x2.4G N
4.9G_PMA E 1-16 CPRI 1x4.9G N
9.8G_PMA E 1-16 CPRI 1x9.8G N
10.1G_PCS E 1-16 CPRI 1x10.1G Y
12.2G_PCS E 1-16 CPRI 1x12.2G Y
24.3G_PCS E 1-16 CPRI 1x24.3G Y
Related Information
1 For E-Tile, when AN/LT is enabled, PTP cannot be enabled for multi-port 10GbE and 25GbE design.
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