Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping 3.4. Analog Parameter Options
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Asynchronous Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status 7.1.21. HSSI Hotplug Debug Port Control 7.1.22. HSSI Hotplug Debug Port Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

3.3. F-Tile Ethernet Port to PMA Channel Mapping

For F-Tile, certain profiles can only be enabled on specific ports. The following table illustrates the Ethernet SS port to PMA channel mapping based on profile.
Table 13.  Ethernet SS Port to PMA Channel Mapping Based on Profile
Configuration Topology #Of ports FGT Q0 (1-32 NRZ ) FGT Q1 (1-32 NRZ, 20-58 PAM4) FGT Q2 (1-32 NRZ, 20-58 PAM4) FGT Q3 (1-32 NRZ, 20-58 PAM4) FHT (24-29 NRZ, 48-58 both, 96-116 PAM4)
FGT0 FGT1 FGT2 FGT3 FGT4 FGT5 FGT6 FGT7 FGT8 FGT9 FGT10 FGT11 FGT12 FGT13 FGT14 FGT15 FHT0 FHT1 FHT2 FHT3
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19
10GbE 15 16 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
10GbE 5/6 0 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) 4 ports available with 400G core
40GbE (XAUI-4) 15 4 P0 P4 P8 P12
40GbE (XAUI-4) 5/6 0 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) 4 ports available with 400G core
25GbE 15 16 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
25GbE 5/6 4 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16 P17 P18 P19
50GAUI-2 (NRZ) 15 8 P0 P2 P4 P6 P8 P10 P12 P14
50GAUI-2 (NRZ) 5/6 2 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16 P18
50GAUI-1 (PAM4) 15 8 8 ports available for 200G PCS with 200G Core or 400G core (max MAC 400G) P8 P9 P10 P11 P12 P13 P14 P15
50GAUI-1 (PAM4) 5 4 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16 P17 P18 P19
100GCAUI-4 (NRZ) 15 4 P0 P4 P8 P12
100GCAUI-4 (NRZ) 5 3 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16
100GAUI-2 (PAM4) 15 4 8 ports available for 200G PCS with 200G Core or 400G core (max MAC 400G) P8 P10 P12 P14
100GAUI-2 (PAM4) 5 2 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16 P18
100GAUI-1 (PAM4) 5 4 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16 P17 P8 P19
200GAUI-8 (NRZ) 15 2 P0 P8
200GAUI-4 (PAM4) 15 2 8 ports available for 200G PCS with 200G Core or 400G core (max MAC 400G) P8 P12
200GAUI-4 (PAM4) 5 1 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16
200GAUI-2 (PAM4) 5 2 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16 P18
400GAUI-8 (PAM4) 15 1 P8
400GAUI-4 (PAM4) 5 1 6/8 ports available for 150/200G PCS with 200G Core only (6 if PTP is enabled on any FHT) P16
Note:
  1. FGT PMA channels supports NRZ rates 1 – 32Gbps, PAM4 rates 20-58Gbps. FHT PMA channels supports NRZ rates 24-29Gbps and 48-58Gbps, and PAM4 rates from 48-58Gbps and 96-116Gbps.
  2. Ethernet SS assumes that the PCIe block is not enabled while determining the available ports for configuration, i.e., the topologies 5,6,10,11,15 are used for determining the available PMA channels and the port’s profile and sub-profile.
  3. Any F-tile topology supports up to 16 ports only. If FHT PMA channels are enabled then FGT quads 2&3 are not available, and also if PTP is also enabled the FGT Quad-1 Channel-2&3 are not available, i.e. if FHT is enabled then 12 channels are available without PTP and 10 are available with PTP.
  4. FHT channels are connected to 400G core only. FGT quad 2&3 are connected to 400G core only. FGT quads 0&1 are connected to both 400G and 200G cores.
  5. FGT Quad-0 is not does not support PAM4 rates. FGT Quad-1 supports PAM4 rates with 200G core only i.e., non MAC+PCS profiles. FGT Quad 2&3 supports PAM4 rates with 400G core only i.e., MAC+PCS rates.
  6. 16 FGT PMA channels are mapped to ports P0 to P15. And the 4 FHT PMA channels are mapped to ports P16-P19. The port to PMA channel mapping is fixed.
  7. FHT ports are disabled if any port from P8-P15 is enabled.
  8. Topology 15 is with 400G core only.
  9. If PTP is enabled – max capacity with 200G core or P0-P7 is 150G only for topology 10&11
  10. If any port from P8-P15 is enabled, then P16-P19 are disabled. Also, P16-P19 are disabled of PTP is enabled on P0-P7.
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